2 // Copyright (c) 2015, Tobias Mueller tm(at)tm3d.de
3 // All rights reserved.
5 // Redistribution and use in source and binary forms, with or without
6 // modification, are permitted provided that the following conditions are
9 // * Redistributions of source code must retain the above copyright
10 // notice, this list of conditions and the following disclaimer.
11 // * Redistributions in binary form must reproduce the above copyright
12 // notice, this list of conditions and the following disclaimer in the
13 // documentation and/or other materials provided with the
15 // * All advertising materials mentioning features or use of this
16 // software must display the following acknowledgement: This product
17 // includes software developed by tm3d.de and its contributors.
18 // * Neither the name of tm3d.de nor the names of its contributors may
19 // be used to endorse or promote products derived from this software
20 // without specific prior written permission.
22 // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
23 // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
24 // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
25 // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
26 // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
27 // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
28 // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
29 // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
30 // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
32 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34 #define F_CPU 8000000UL
36 #include <avr/interrupt.h>
37 #include <util/delay.h>
39 #include <avr/sleep.h>
40 #include <avr/pgmspace.h>
44 //const float k_rs[54] PROGMEM ={0.000000,24.125000,48.585366,72.731707,96.829268,121.097561,145.700000,170.600000,195.650000,220.625000,245.365854,269.853659,294.119048,318.195122,342.166667,366.000000,389.761905,413.428571,437.023810,460.558140,484.047619,507.511628,530.976190,554.418605,577.883721,601.395349,624.952381,648.571429,672.285714,696.073171,719.976190,744.000000,768.146341,792.439024,816.853659,841.414634,866.125000,890.975000,916.000000,941.179487,966.525000,992.025641,1017.717949,1043.589744,1069.657895,1095.945946,1122.432432,1149.184211,1176.189189,1203.472222,1231.083333,1259.000000,1287.285714,1315.941176};
45 const float j_rs[70] PROGMEM ={0, 18.302913, 34.830476, 50.783019, 70.653704, 90.505455, 110.341818, 130.165455, 149.163636, 160.791071, 180.596364, 200.398214, 220.200000, 240.000000, 250.882883, 270.603636, 290.409091, 310.216364, 330.025455, 342.472727, 360.649091, 380.461818, 400.275000, 420.087273, 435.275676, 450.703636, 470.503636, 490.298214, 510.082456, 523.486726, 540.621053, 560.370175, 580.105172, 591.979487, 610.527119, 630.213559, 644.601653, 660.534426, 680.168852, 690.787097, 710.391935, 729.123810, 740.559375, 760.126562, 770.684615, 790.235385, 800.782812, 820.331250, 834.681250, 850.446032, 870.017460, 880.600000, 900.196774, 911.099187, 930.432787, 950.073333, 960.728333, 980.396667, 1000.078333, 1010.772881, 1030.475862, 1050.187931, 1065.717241, 1080.631034, 1100.358621, 1120.089655, 1131.840000,1150.556897, 1170.294737, 1190.035088};
46 double gettemp_rs(double V) {
47 uint8_t iv=(uint8_t)(V);
48 float t0=pgm_read_float(&(j_rs[iv]));
49 float t1=pgm_read_float(&(j_rs[iv+1]));
50 return t0+(t1-t0)/1*(V-iv);
54 uint8_t owid[8]={0x28, 0xA2, 0xD9, 0x84, 0x00, 0x16, 0x02, 0xAC};/**/
55 uint8_t config_info[16]={0x02,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x02,0x00,0x00,0x00,0x00,0x00,0x00,0x00};
58 #error "Variable not correct"
62 extern uint8_t gcontrol;
63 extern uint8_t reset_indicator;
64 extern uint8_t alarmflag;
67 volatile uint8_t wdcounter;
71 volatile uint8_t bytes[8];
87 #if defined(__AVR_ATtiny24__)||defined(__AVR_ATtiny44__) || defined(__AVR_ATtiny84__) || defined(__AVR_ATtiny24A__)||defined(__AVR_ATtiny44A__) || defined(__AVR_ATtiny84A__)
92 //sleep_disable(); // Disable Sleep on Wakeup
94 if (reset_indicator==1) reset_indicator++;
95 else if (reset_indicator==2) mode=0;
102 //sleep_enable(); // Enable Sleep Mode
107 #define OWM_PORT PORTA
109 #define OWM_PINN PINA0
112 #define OWM_SET_LOW OWM_PORT&=~(1<<OWM_PINN);OWM_DD|=(1<<OWM_PINN)
113 #define OWM_SET_HIGH OWM_DD&=~(1<<OWM_PINN);OWM_PORT|=(1<<OWM_PINN)
115 #define OWM_IS_LOW ((OWM_PIN & (1<<OWM_PINN))==0)
119 OWM_PORT|=(1<<OWM_PINN); //PULL UP
120 OWM_DD&=~(1<<OWM_PINN);
123 #define owm_delay(us1) _delay_us(us1)
125 uint8_t owm_reset() {
130 if (OWM_IS_LOW) {owm_delay(420); return 1;} else {owm_delay(420); return 0;}
135 void owm_rw(uint8_t *b) {
159 void owm_block(uint8_t count, uint8_t *buf){
161 for(i=0;i<count;i++) {
166 inline int16_t ow_fconvert(uint8_t b1, uint8_t b2) {
168 tsht=b1 |((int)b2<<8);
173 volatile double V,ktemp;
178 while ((ADCSRA&(1<<ADSC)));
183 //PRR|=(1<<PRUSI)|(1<<PRADC); //Switch off usi and adc for save Power
191 PORTA=0xFF-(1<<PINA1)-(1<<PINA2);
195 MCUCR &=~(1<<PUD); //All Pins Pullup...
198 WDTCSR |= ((1<<WDCE) ); // Enable the WD Change Bit//| (1<<WDE)
199 WDTCSR |= (1<<WDIE) | // Enable WDT Interrupt
200 (1<<WDP2) | (1<<WDP1); // Set Timeout to ~1 seconds
204 ADCSRA=(1<<ADEN)|(1<<ADPS2)|(1<<ADPS1)|(1<<ADPS0);
215 for(uint8_t i=1;i<9;i++) {
220 if (block[1]==0x28) { //DS18B20 angeschlossen
221 for(uint8_t i=0;i<8;i++) {
224 while(EECR & (1<<EEPE));
227 if (EEDR!=0x28) { //Wenn keine ID im Eeprom uebernimm es
228 for(uint8_t a=0;a<8;a++) {
229 while(EECR & (1<<EEPE));
230 EECR = (0<<EEPM1)|(0<<EEPM0);
239 uint16_t ares[16],sum;
241 ares[0]=0;//ADmess();
242 for (par=1;par<16;par++) {
259 for(uint8_t i=0;i<16;i++) {
262 V=sum/20.0/1024.0*1.174*1000.0/16.0;
263 //V=sum/20.0/1024.0*1.01*1000.0/16.0;
273 for(uint8_t i=0;i<9;i++) block[i+2]=0xFF;
276 if (PINB&(1<<PINB0)) {
277 htemp=(ktemp*16+(block[2]|(block[3]<<8)))/10;
280 htemp=ktemp*16+(block[2]|(block[3]<<8));
282 uint8_t t8=pack.temp>>4;
284 if (t8>pack.TH) af=1;
285 if (t8<=pack.TL) af=1;
295 #if defined(__AVR_ATtiny25__)||defined(__AVR_ATtiny45__) || defined(__AVR_ATtiny85__)
296 if (((TIMSK & (1<<TOIE0))==0)&& (mode==0))
298 #if defined(__AVR_ATtiny24__)||defined(__AVR_ATtiny44__) || defined(__AVR_ATtiny84__) ||defined(__AVR_ATtiny24A__)||defined(__AVR_ATtiny44A__) || defined(__AVR_ATtiny84A__)
299 if (((TIMSK0 & (1<<TOIE0))==0)&& (mode==0))
302 // CLKPR=(1<<CLKPCE);
303 // CLKPR=(1<<CLKPS2); /*0.5Mhz*/
304 // PORTB&=~(1<<PINB1);
305 MCUCR|=(1<<SE)|(1<<SM1);