1 // Copyright (c) 2015, Tobias Mueller tm(at)tm3d.de
2 // All rights reserved.
4 // Redistribution and use in source and binary forms, with or without
5 // modification, are permitted provided that the following conditions are
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11 // notice, this list of conditions and the following disclaimer in the
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15 // software must display the following acknowledgement: This product
16 // includes software developed by tm3d.de and its contributors.
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19 // without specific prior written permission.
21 // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22 // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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39 .macro cljmp val,addr; Weiter sprung, wenn das ziel zu weit entfernt fuer brxx
46 .macro cset val,mod ;Nur der Mode wird gesetzt. Abkuerzung da oft nur das noch bleibt
58 #define OW_READ_ROM_COMMAND 1
60 #define OW_SEARCHROMS 3 ;next send two bit
61 #define OW_SEARCHROMR 4 ; next resive master answer
62 #define OW_READ_COMMAND1 5
63 #define OW_READ_COMMAND2 6
64 #define OW_FWCONFIGINFO1 7
65 #define OW_FWCONFIGINFO2 8
68 #ifdef _CHANGEABLE_ID_
69 #define OW_WRITE_NEWID 9
70 #define OW_READ_NEWID 10
71 #define OW_SET_NEWID 11
72 #define OW_FIRST_COMMAND 12
76 .macro CHANGE_ID_COMMANDS
77 cset 0x75,OW_WRITE_NEWID
78 cljmp 0xA7,hrc_set_readid
79 cljmp 0x79,hrc_set_setid
84 #define OW_FIRST_COMMAND 9
88 ; test auf run flasher command 0x88 in h_readcommand
93 1: ldi r_temp,0 ;Anderes Kommando flashmarker zuruecksetzen...
94 sts flashmarker,r_temp
99 .macro FW_CONFIG_INFO1
100 cljmp 0x85,hrc_fw_configinfo1
102 .macro FW_CONFIG_INFO2
103 cljmp 0x85,hrc_fw_configinfo2
106 #ifdef _CHANGEABLE_ID_
107 ; lesen der ID aus dem EEPROM beim Start
109 ldi r_temp2,lo8(E2END)
112 out _SFR_IO_ADDR(EEARH), zh
116 rjmp read_EEPROM_ID_loop
118 ldi r_temp2,lo8(E2END)
121 out _SFR_IO_ADDR(EEARH), zh
126 sbic _SFR_IO_ADDR(EECR), EEPE
127 rjmp read_EEPROM_ID_loop
128 out _SFR_IO_ADDR(EEARL),r_temp2
129 sbi _SFR_IO_ADDR(EECR), EERE
130 in r_rwbyte,_SFR_IO_ADDR(EEDR)
132 breq read_EEPROM_ID_end
137 brne read_EEPROM_ID_loop
149 rjmp handle_end_no_bcount // sleep eventuell reset, nichts tun und auf Timeout warten
150 rjmp h_readromcommand
158 #ifdef _CHANGEABLE_ID_
169 cjmp 0x55,hrc_set_matchrom
170 cjmp 0xF0,hrc_set_searchrom
171 cjmp 0xEC,hrc_set_alarm_search
173 rjmp handle_end_sleep
178 lds r_temp,flashmarker
180 brne hrc_jmp_flasher_inc
185 ret ; Direkter Sprung zum Bootloader
188 sts flashmarker,r_temp
189 rjmp handle_end_sleep
194 sts srbyte,r_temp ; Beide geraete nehmen an searchrom teil
195 ldi r_mode,OW_MATCHROM
202 sts srbyte,r_temp ; Beide geraete nehmen an searchrom teil
203 configZ idtable,r_bytep
204 rjmp h_searchrom_next_bit
206 hrc_start_read_command: ;Skip rom und Matchrom ok...
209 breq hrc_start_read_command1
211 breq hrc_start_read_command2
212 rjmp handle_end_sleep
214 hrc_start_read_command1:
215 ldi r_mode,OW_READ_COMMAND1
217 hrc_start_read_command2:
218 ldi r_mode,OW_READ_COMMAND2
222 hrc_set_alarm_search:
225 brne hrc_set_searchrom ;alarm flag nicht 0 also gehe zu searchrom
227 rjmp handle_end_sleep
230 ldi r_mode,OW_FWCONFIGINFO1
236 ldi r_mode,OW_FWCONFIGINFO2
242 ;---------------------------------------------------
244 ;---------------------------------------------------
249 sbrs r_bcount,0 ;ueberspringe wenn bit 1 =0 also geraet 1 nich mehr im rennen
251 configZ owid1,r_bytep
255 cbr r_bcount,1 ; loesche geraet
256 breq h_matchrom_sleep
258 configZ owid2,r_bytep
262 cbr r_bcount,2 ; loesche geraet
263 breq h_matchrom_sleep
268 breq hrc_start_read_command ;Starten von Read Command
273 rjmp handle_end_sleep
276 ;---------------------------------------------------
278 ;---------------------------------------------------
281 h_searchrom_next_bit: ;Setup next Bit of ID
283 lds r_temp,srbyte ;srbyte ist ein zeiger auf die bits fuer ein bit im Table
284 h_searchrom_next_bit_l2:
286 breq h_searchrom_next_bit_l1
290 rjmp h_searchrom_next_bit_l2
291 h_searchrom_next_bit_l1:
293 rol r_rwbyte ; negiertes bit in rwbyte
295 rol r_rwbyte ; bit in rwbyte
297 ldi r_bcount,0x40 ; zwei bits sensden dann zu Searchromr
298 ldi r_mode,OW_SEARCHROMR
299 rjmp handle_end_no_bcount
303 h_searchroms: ; Modus Send zwei bit
304 configZ idtable,r_bytep
308 breq h_searchroms_idd
310 breq h_searchroms_id1
312 breq h_searchroms_id2
313 rjmp handle_end_sleep ; zur Sicherheit.....
316 breq h_searchroms_idd_zero
318 sbrc r_temp2,0 ;springe wenn nicht beide bits 0 (id 1 negiert und id 2 negiert)
319 rjmp handle_end_sleep ;
320 sbrc r_temp2,4 ;id1 set? then skip
321 cbr r_temp,1 ; loesche bit 1 in srbyte
322 sbrc r_temp2,2 ; springe wenn id 2 gesetzt ist
323 cbr r_temp,2 ; loesche bit 2 in srbyte
325 rjmp h_searchroms_idX_end
326 h_searchroms_idd_zero:
327 sbrc r_temp2,1 ;springe wenn nicht beide 1 (id 1 und id 2 )
328 rjmp handle_end_sleep ;beide 1 gehe schlafen
329 sbrs r_temp2,4 ;id1 0? then skip
330 cbr r_temp,1 ; loesche bit 1 in srbyte
331 sbrs r_temp2,2 ; springe wenn id 2 null ist
332 cbr r_temp,2 ; loesche bit 2 in srbyte
334 rjmp h_searchroms_idX_end
337 breq h_searchroms_id1_zero
339 sbrs r_temp2,5 ;id1 set? then skip
340 rjmp handle_end_sleep ;
341 rjmp h_searchroms_idX_end
342 h_searchroms_id1_zero:
343 sbrs r_temp2,4 ;id1 set? then skip
344 rjmp handle_end_sleep ;
345 rjmp h_searchroms_idX_end
348 breq h_searchroms_id2_zero
350 sbrs r_temp2,3 ;id1 set? then skip
351 rjmp handle_end_sleep ;
352 rjmp h_searchroms_idX_end
353 h_searchroms_id2_zero:
354 sbrs r_temp2,2 ;id1 set? then skip
355 rjmp handle_end_sleep ;
356 rjmp h_searchroms_idX_end
357 h_searchroms_idX_end:
360 brne h_searchroms_idX_end1
361 rjmp handle_end_sleep
362 h_searchroms_idX_end1:
365 breq h_searchrom_end_ok ;unterschied nur das letzt bit wird wohl nie vorkommen
366 rjmp h_searchrom_next_bit
370 rjmp hrc_start_read_command
372 h_searchromr: ; stelle um auf empfangen
374 ldi r_mode,OW_SEARCHROMS
375 ldi r_bcount,0 ;gehe nach einem bit zu SEARCHROMS
376 rjmp handle_end_no_bcount
379 ;---------------------------------------------------
381 ;---------------------------------------------------
384 configZ config_info1,r_bytep
385 rjmp h_fwconfiginfo_go
387 configZ config_info2,r_bytep
391 breq h_fwconfiginfo_crc
394 breq h_fwconfiginfo_all
395 #elif defined _CRC16_
397 breq h_fwconfiginfo_crc2
399 breq h_fwconfiginfo_all
402 breq h_fwconfiginfo_all
403 #warning No CRC known code implemented
414 rjmp handle_end_sleep
417 ;---------------------------------------------------
418 ; CHANGE ROM FUNCTIONS
419 ;---------------------------------------------------
422 #ifdef _CHANGEABLE_ID_
425 configZ newid,r_bytep
431 rjmp handle_end_sleep
435 ldi r_mode,OW_READ_NEWID
440 configZ newid,r_bytep
445 rjmp handle_end_sleep
448 ldi r_mode,OW_SET_NEWID
449 ;ldi r_bytep,1 ;start to write in 2
450 rjmp handle_end_inc ;set r_bytep to 1!!!
457 configZ owid1,r_bytep
460 configZ owid2,r_bytep
464 brne h_setid_bad_code_all
471 rjmp h_setid_bad_code_all ;sollte eigentlich nicht passieren
479 ldi r_temp2,lo8(E2END)
485 ;ldi r_temp,0 ;kommt nicht vor das ein E2ROM genau n*256+(0 bis 7) byte gross ist
487 out _SFR_IO_ADDR(EEARH),zh
491 h_setid_EEPROM_write:
492 sbic _SFR_IO_ADDR(EECR), EEPE
493 rjmp h_setid_EEPROM_write
494 ldi r_temp, (0<<EEPM1)|(0<<EEPM0)
495 out _SFR_IO_ADDR(EECR), r_temp
496 ;nur adresse L schreiben H bleibt aus oben genannten grund gleich.
497 out _SFR_IO_ADDR(EEARL),r_temp2
499 out _SFR_IO_ADDR(EEDR), r_rwbyte
500 sbi _SFR_IO_ADDR(EECR), EEMPE
501 sbi _SFR_IO_ADDR(EECR), EEPE
505 brne h_setid_EEPROM_write
506 //rcall read_EEPROM_ID1
507 //rcall read_EEPROM_ID2
525 h_setid_bad_code_all:
526 rjmp handle_end_sleep
544 ; check for bootloader jumper
545 ;vor allen anderen Registerconfigs
547 ldi r_temp,(1<<PUD) ;enable pullup
548 out _SFR_IO_ADDR(MCUCR) ,r_temp
549 sbi _SFR_IO_ADDR(PORTA),PINA5 ;internal pullup on PINA5
550 sbi _SFR_IO_ADDR(PORTA),PINA4 ;internal pullup on PINA4
552 sbis _SFR_IO_ADDR(PINA),PINA5
553 rjmp owinit_botest_end ;PinA5 nicht auf 1
554 sbis _SFR_IO_ADDR(PINA),PINA4
555 rjmp owinit_botest_end ;PinA4 nicht auf 1
556 cbi _SFR_IO_ADDR(PORTA),PINA4
557 sbi _SFR_IO_ADDR(DDRA),PINA4 ;PINA4 AUSGANG und 0
559 sbic _SFR_IO_ADDR(PINA),PINA5
560 rjmp owinit_botest_end ;PINA5 nicht 0.... nicht verbunden
561 cbi _SFR_IO_ADDR(DDRA),PINA4
566 ret ; Direkter Sprung zum Bootloader*/
569 HW_INIT //Microcontroller specific
570 CHIP_INIT //1-Wire device specific
571 #ifdef _CHANGEABLE_ID_
573 rcall read_EEPROM_ID1
574 rcall read_EEPROM_ID2
599 rol r_mode ;6. Bit id1
601 rol r_mode ; 5. Bit id1negiert
603 rol r_mode ;;4. Bit id2
605 rol r_mode ;3. Bit id2 negiert
607 rol r_mode ;zweites bit id1 und id2
609 rol r_mode ;erstes bit id1 negiert und id2 negiert
615 ;copy ids in config bytes
618 ldi yl,lo8(config_info2+9)
619 ldi yh,hi8(config_info2+9)
625 brne owinit_cpconfig1
628 ldi yl,lo8(config_info1+9)
629 ldi yh,hi8(config_info1+9)
635 brne owinit_cpconfig2
650 sts mode,r_temp ;SLEEP