1 // Copyright (c) 2015, Tobias Mueller tm(at)tm3d.de
2 // All rights reserved.
4 // Redistribution and use in source and binary forms, with or without
5 // modification, are permitted provided that the following conditions are
8 // * Redistributions of source code must retain the above copyright
9 // notice, this list of conditions and the following disclaimer.
10 // * Redistributions in binary form must reproduce the above copyright
11 // notice, this list of conditions and the following disclaimer in the
12 // documentation and/or other materials provided with the
14 // * All advertising materials mentioning features or use of this
15 // software must display the following acknowledgement: This product
16 // includes software developed by tm3d.de and its contributors.
17 // * Neither the name of tm3d.de nor the names of its contributors may
18 // be used to endorse or promote products derived from this software
19 // without specific prior written permission.
21 // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22 // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
23 // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
24 // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
25 // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
26 // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
27 // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
28 // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
29 // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30 // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
31 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 #define OW_PORT _SFR_IO_ADDR(PORTB) //1 Wire Port
37 #define OW_PIN _SFR_IO_ADDR(PINB) //1 Wire Pin as number
38 #define OW_PINN PORTB2
39 #define OW_DDR _SFR_IO_ADDR(DDRB) //pin direction register
40 #define TCNT_REG _SFR_IO_ADDR(TCNT0)
42 #define DB_PORT _SFR_IO_ADDR(PORTB) //1 Wire Port
43 #define DB_PIN _SFR_IO_ADDR(PINB) //1 Wire Pin as number
44 #define DB_PINN PORTB1
46 #define SETZEROMARKER sbi _SFR_IO_ADDR(DDRB),5
47 #define RESETZEROMARKER cbi _SFR_IO_ADDR(DDRB),5
48 #define TESTZEROMARKER sbic _SFR_IO_ADDR(DDRB),5
50 ;#define sdb sbi _SFR_IO_ADDR(PORTB),1
51 ;#define cdb cbi _SFR_IO_ADDR(PORTB),1
53 #define TIMER_INTERRUPT TIM0_OVF_vect
54 #define PIN_INTERRIPT INT0_vect
58 #define OWT_MIN_RESET 70
60 #define OWT_RESET_PRESENT 15
61 #define OWT_PRESENT 50
67 #define OWT_MIN_RESET 140
69 #define OWT_RESET_PRESENT 30
70 #define OWT_PRESENT 130
79 out _SFR_IO_ADDR(TIFR),r_temp
83 in r_temp, _SFR_IO_ADDR(TIFR)
84 sbrc r_temp,TOV0 ; wenn ueberlauf gleiich weiter
87 .macro CLEAR_INTERRUPT_FLAG
88 ldi r_temp,(1<<INTF0);inerrupt flags durch 1 loeschen..... 0 macht nix
89 out _SFR_IO_ADDR(GIFR),r_temp
93 in r_temp,_SFR_IO_ADDR(TIMSK)
95 out _SFR_IO_ADDR(TIMSK),r_temp
96 ldi r_temp,(1<<TOV0) ;inerrupt flags durch 1 loeschen..... 0 macht nix
97 out _SFR_IO_ADDR(TIFR),r_temp
101 in r_temp,_SFR_IO_ADDR(TIMSK)
102 cbr r_temp,(1<<TOIE0)
103 out _SFR_IO_ADDR(TIMSK),r_temp
108 in r_temp,_SFR_IO_ADDR(MCUCR)
109 ori r_temp,(1<<ISC01)
110 out _SFR_IO_ADDR(MCUCR),r_temp
114 .macro SET_FALLING_RESET_SLEEP
115 in r_temp,_SFR_IO_ADDR(MCUCR)
116 ori r_temp,(1<<ISC01)
117 andi r_temp,~(1<<SM1)
118 out _SFR_IO_ADDR(MCUCR),r_temp
125 out _SFR_IO_ADDR(CLKPR),r_temp
127 ldi r_temp,(1<<CLKPS0)
131 out _SFR_IO_ADDR(CLKPR),r_temp
134 out _SFR_IO_ADDR(TIMSK),r_temp ;; is default
137 out _SFR_IO_ADDR(GIMSK),r_temp
138 ;Set Timerclock to Clock / 8 (2us)
140 out _SFR_IO_ADDR(TCCR0B),r_temp
142 cbi OW_DDR,OW_PINN ;; is default....
144 ldi r_temp,(1<<ISC01)
145 out _SFR_IO_ADDR(MCUCR),r_temp