1 /*****************************************************************************
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5 * File : USI_TWI_Master.h
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6 * Compiler : AVRGCC Toolchain version 3.4.2
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7 * Revision : $Revision: 992 $
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8 * Date : $Date: 2013-11-07 $
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9 * Updated by : $Author: Atmel $
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11 * Support mail : avr@atmel.com
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13 * Supported devices : All device with USI module can be used.
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14 * The example is written for the ATmega169, ATtiny26 and ATtiny2313
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16 * AppNote : AVR310 - Using the USI module as a TWI Master
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18 * Description : This is an implementation of an TWI master using
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19 * the USI module as basis. The implementation assumes the AVR to
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20 * be the only TWI master in the system and can therefore not be
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21 * used in a multi-master system.
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22 * Usage : Initialize the USI module by calling the USI_TWI_Master_Initialise()
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23 * function. Hence messages/data are transceived on the bus using
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24 * the USI_TWI_Start_Transceiver_With_Data() function. If the transceiver
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25 * returns with a fail, then use USI_TWI_Get_Status_Info to evaluate the
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26 * couse of the failure.
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28 ****************************************************************************/
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30 //********** Defines **********//
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32 // Defines controlling timing limits
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33 #define TWI_FAST_MODE
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35 #define SYS_CLK 8000.0 // [kHz]
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37 #ifdef TWI_FAST_MODE // TWI FAST mode timing limits. SCL = 100-400kHz
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38 #define T2_TWI ((SYS_CLK *1300) /1000000) +1 // >1,3us
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39 #define T4_TWI ((SYS_CLK * 600) /1000000) +1 // >0,6us
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41 #else // TWI STANDARD mode timing limits. SCL <= 100kHz
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42 #define T2_TWI ((SYS_CLK *4700) /1000000) +1 // >4,7us
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43 #define T4_TWI ((SYS_CLK *4000) /1000000) +1 // >4,0us
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46 // Defines controling code generating
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47 //#define PARAM_VERIFICATION
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48 //#define NOISE_TESTING
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49 //#define SIGNAL_VERIFY
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51 //USI_TWI messages and flags and bit masks
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54 /****************************************************************************
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55 Bit and byte definitions
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56 ****************************************************************************/
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57 #define TWI_READ_BIT 0 // Bit position for R/W bit in "address byte".
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58 #define TWI_ADR_BITS 1 // Bit position for LSB of the slave address bits in the init byte.
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59 #define TWI_NACK_BIT 0 // Bit position for (N)ACK bit.
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61 #define USI_TWI_NO_DATA 0x00 // Transmission buffer is empty
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62 #define USI_TWI_DATA_OUT_OF_BOUND 0x01 // Transmission buffer is outside SRAM space
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63 #define USI_TWI_UE_START_CON 0x02 // Unexpected Start Condition
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64 #define USI_TWI_UE_STOP_CON 0x03 // Unexpected Stop Condition
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65 #define USI_TWI_UE_DATA_COL 0x04 // Unexpected Data Collision (arbitration)
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66 #define USI_TWI_NO_ACK_ON_DATA 0x05 // The slave did not acknowledge all data
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67 #define USI_TWI_NO_ACK_ON_ADDRESS 0x06 // The slave did not acknowledge the address
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68 #define USI_TWI_MISSING_START_CON 0x07 // Generated Start Condition not detected on bus
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69 #define USI_TWI_MISSING_STOP_CON 0x08 // Generated Stop Condition not detected on bus
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71 // Device dependant defines
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73 #if defined(__AVR_AT90Mega169__) | defined(__AVR_ATmega169PA__) | \
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74 defined(__AVR_AT90Mega165__) | defined(__AVR_ATmega165__) | \
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75 defined(__AVR_ATmega325__) | defined(__AVR_ATmega3250__) | \
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76 defined(__AVR_ATmega645__) | defined(__AVR_ATmega6450__) | \
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77 defined(__AVR_ATmega329__) | defined(__AVR_ATmega3290__) | \
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78 defined(__AVR_ATmega649__) | defined(__AVR_ATmega6490__)
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79 #define DDR_USI DDRE
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80 #define PORT_USI PORTE
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81 #define PIN_USI PINE
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82 #define PORT_USI_SDA PORTE5
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83 #define PORT_USI_SCL PORTE4
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84 #define PIN_USI_SDA PINE5
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85 #define PIN_USI_SCL PINE4
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88 #if defined(__AVR_ATtiny25__) | defined(__AVR_ATtiny45__) | defined(__AVR_ATtiny85__) | \
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89 defined(__AVR_AT90Tiny26__) | defined(__AVR_ATtiny26__)
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90 #define DDR_USI DDRB
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91 #define PORT_USI PORTB
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92 #define PIN_USI PINB
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93 #define PORT_USI_SDA PORTB0
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94 #define PORT_USI_SCL PORTB2
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95 #define PIN_USI_SDA PINB0
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96 #define PIN_USI_SCL PINB2
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99 #if defined(__AVR_AT90Tiny2313__) | defined(__AVR_ATtiny2313__)
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100 #define DDR_USI DDRB
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101 #define PORT_USI PORTB
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102 #define PIN_USI PINB
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103 #define PORT_USI_SDA PORTB5
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104 #define PORT_USI_SCL PORTB7
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105 #define PIN_USI_SDA PINB5
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106 #define PIN_USI_SCL PINB7
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109 #if defined(__AVR_ATtiny84__) | defined(__AVR_ATtiny84A__)
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110 #define DDR_USI DDRA
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111 #define PORT_USI PORTA
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112 #define PIN_USI PINA
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113 #define PORT_USI_SDA PORTA6
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114 #define PORT_USI_SCL PORTA4
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115 #define PIN_USI_SDA PINA6
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116 #define PIN_USI_SCL PINA4
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123 #define ACK (1<<TWI_NACK_BIT )
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127 //********** Prototypes **********//
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129 void USI_TWI_Master_Initialise( void );
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130 unsigned char USI_TWI_Start_Transceiver_With_Data( unsigned char * , unsigned char );
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131 unsigned char USI_TWI_Get_State_Info( void );
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133 unsigned char I2c_WriteByte(unsigned char msg);
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134 unsigned char I2c_ReadByte(unsigned char ack_mode);
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135 void I2c_StartCondition(void);
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136 void I2c_StopCondition(void);
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