1 // Copyright (c) 2015, Tobias Mueller tm(at)tm3d.de
2 // All rights reserved.
4 // Redistribution and use in source and binary forms, with or without
5 // modification, are permitted provided that the following conditions are
8 // * Redistributions of source code must retain the above copyright
9 // notice, this list of conditions and the following disclaimer.
10 // * Redistributions in binary form must reproduce the above copyright
11 // notice, this list of conditions and the following disclaimer in the
12 // documentation and/or other materials provided with the
14 // * All advertising materials mentioning features or use of this
15 // software must display the following acknowledgement: This product
16 // includes software developed by tm3d.de and its contributors.
17 // * Neither the name of tm3d.de nor the names of its contributors may
18 // be used to endorse or promote products derived from this software
19 // without specific prior written permission.
21 // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22 // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
23 // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
24 // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
25 // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
26 // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
27 // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
28 // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
29 // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30 // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
31 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34 #define OW_PORT _SFR_IO_ADDR(PORTB) //1 Wire Port
35 #define OW_PIN _SFR_IO_ADDR(PINB) //1 Wire Pin as number
36 #define OW_PINN PORTB2
37 #define OW_DDR _SFR_IO_ADDR(DDRB) //pin direction register
38 #define TCNT_REG _SFR_IO_ADDR(TCNT0)
40 #define DB_PORT _SFR_IO_ADDR(PORTB) //DEBUG
41 #define DB_PIN _SFR_IO_ADDR(PINB) //DEBUG
42 #define DB_DDR _SFR_IO_ADDR(DDRB) //DEBUG
43 #define DB_PINN PORTB1
45 #define SETZEROMARKER sbi _SFR_IO_ADDR(DDRB),3
46 #define RESETZEROMARKER cbi _SFR_IO_ADDR(DDRB),3
47 #define TESTZEROMARKER sbic _SFR_IO_ADDR(DDRB),3
49 //#define sdb sbi _SFR_IO_ADDR(PORTB),DB_PINN
50 //#define cdb cbi _SFR_IO_ADDR(PORTB),DB_PINN
52 #define TIMER_INTERRUPT TIM0_OVF_vect
53 #define PIN_INTERRIPT EXT_INT0_vect
56 //#define OWT_MIN_RESET 160
57 //#define OWT_RESET2 40
58 //#define OWT_RESET_PRESENT 15
59 //#define OWT_PRESENT 50
60 //#define OWT_WRITE 18
63 #define OWT_MIN_RESET 80
64 #define OWT_RESET2 100
65 #define OWT_RESET_PRESENT 30
66 #define OWT_PRESENT 130
72 .macro CLEAR_INTERRUPT_FLAG
73 ldi r_temp,(1<<INTF0);inerrupt flags durch 1 loeschen..... 0 macht nix
74 out _SFR_IO_ADDR(GIFR),r_temp
78 in r_temp,_SFR_IO_ADDR(TIMSK0)
80 out _SFR_IO_ADDR(TIMSK0),r_temp
81 ldi r_temp,(1<<TOV0) ;inerrupt flags durch 1 loeschen..... 0 macht nix
82 out _SFR_IO_ADDR(TIFR0),r_temp
86 in r_temp,_SFR_IO_ADDR(TIMSK0)
88 out _SFR_IO_ADDR(TIMSK0),r_temp
91 .macro SET_FALLING_RESET_SLEEP
92 in r_temp,_SFR_IO_ADDR(MCUCR)
95 out _SFR_IO_ADDR(MCUCR),r_temp
101 out _SFR_IO_ADDR(CLKPR),r_temp
102 //ldi r_temp,(1<<CLKPS0)
104 out _SFR_IO_ADDR(CLKPR),r_temp
107 out _SFR_IO_ADDR(TIMSK0),r_temp ;; is default
110 out _SFR_IO_ADDR(GIMSK),r_temp
111 ;Set Timerclock to Clock / 8 (2us bei 4MHz) bzw 1us bei 8 MHz
113 out _SFR_IO_ADDR(TCCR0B),r_temp
115 cbi OW_DDR,OW_PINN ;; is default....
116 cbi OW_PORT,OW_PINN ;; vereinfachung im Hauptprogram (PORTB=0xFF) wegen pullup
118 ldi r_temp,(1<<ISC01)
119 out _SFR_IO_ADDR(MCUCR),r_temp