X-Git-Url: http://git.smho.de/gw/?p=owSlave2.git;a=blobdiff_plain;f=common%2FI2C%2FTWI_Master.h;fp=common%2FI2C%2FTWI_Master.h;h=327b2a537265bdb60a6aed8455a11fcd2381691d;hp=0000000000000000000000000000000000000000;hb=81a79648a168a1167c5ad97d4068621c1751a353;hpb=6467d8138460abffd9ddabc7b0a9f00c764af19c

diff --git a/common/I2C/TWI_Master.h b/common/I2C/TWI_Master.h
new file mode 100644
index 0000000..327b2a5
--- /dev/null
+++ b/common/I2C/TWI_Master.h
@@ -0,0 +1,147 @@
+#ifndef TWI_MASTER_H
+#define TWI_MASTER_H
+#include<avr/io.h> 
+//********** Defines **********//
+
+// Defines controlling timing limits
+#define TWI_FAST_MODE
+#ifdef  __4MHZ__
+#define SYS_CLK  4000.0  // [kHz]
+#else
+#define SYS_CLK   8000.0  // [kHz]
+#endif
+
+
+
+#ifdef TWI_FAST_MODE               // TWI FAST mode timing limits. SCL = 100-400kHz
+  #define T2_TWI    ((SYS_CLK *1300) /1000000) +1 // >1,3us
+  #define T4_TWI    ((SYS_CLK * 600) /1000000) +1 // >0,6us
+  
+#else                              // TWI STANDARD mode timing limits. SCL <= 100kHz
+  #define T2_TWI    ((SYS_CLK *4700) /1000000) +1 // >4,7us
+  #define T4_TWI    ((SYS_CLK *4000) /1000000) +1 // >4,0us
+#endif
+
+// Defines controling code generating
+//#define PARAM_VERIFICATION
+//#define NOISE_TESTING
+//#define SIGNAL_VERIFY
+
+//USI_TWI messages and flags and bit masks
+//#define SUCCESS   7
+//#define MSG       0
+/****************************************************************************
+  Bit and byte definitions
+****************************************************************************/
+#define TWI_READ_BIT  0       // Bit position for R/W bit in "address byte".
+#define TWI_ADR_BITS  1       // Bit position for LSB of the slave address bits in the init byte.
+#define TWI_NACK_BIT  0       // Bit position for (N)ACK bit.
+
+#define USI_TWI_NO_DATA             0x00  // Transmission buffer is empty
+#define USI_TWI_DATA_OUT_OF_BOUND   0x01  // Transmission buffer is outside SRAM space
+#define USI_TWI_UE_START_CON        0x02  // Unexpected Start Condition
+#define USI_TWI_UE_STOP_CON         0x03  // Unexpected Stop Condition
+#define USI_TWI_UE_DATA_COL         0x04  // Unexpected Data Collision (arbitration)
+#define USI_TWI_NO_ACK_ON_DATA      0x05  // The slave did not acknowledge  all data
+#define USI_TWI_NO_ACK_ON_ADDRESS   0x06  // The slave did not acknowledge  the address
+#define USI_TWI_MISSING_START_CON   0x07  // Generated Start Condition not detected on bus
+#define USI_TWI_MISSING_STOP_CON    0x08  // Generated Stop Condition not detected on bus
+
+// Device dependant defines
+
+#if defined(__AVR_AT90Mega169__) | defined(__AVR_ATmega169PA__) | \
+    defined(__AVR_AT90Mega165__) | defined(__AVR_ATmega165__) | \
+    defined(__AVR_ATmega325__) | defined(__AVR_ATmega3250__) | \
+    defined(__AVR_ATmega645__) | defined(__AVR_ATmega6450__) | \
+    defined(__AVR_ATmega329__) | defined(__AVR_ATmega3290__) | \
+    defined(__AVR_ATmega649__) | defined(__AVR_ATmega6490__)
+    #define DDR_USI             DDRE
+    #define PORT_USI            PORTE
+    #define PIN_USI             PINE
+    #define PORT_USI_SDA        PORTE5
+    #define PORT_USI_SCL        PORTE4
+    #define PIN_USI_SDA         PINE5
+    #define PIN_USI_SCL         PINE4
+#endif
+
+#if defined(__AVR_ATtiny25__) | defined(__AVR_ATtiny45__) | defined(__AVR_ATtiny85__) | \
+    defined(__AVR_AT90Tiny26__) | defined(__AVR_ATtiny26__)
+    #define DDR_USI             DDRB
+    #define PORT_USI            PORTB
+    #define PIN_USI             PINB
+    #define PORT_USI_SDA        PORTB0
+    #define PORT_USI_SCL        PORTB2
+    #define PIN_USI_SDA         PINB0
+    #define PIN_USI_SCL         PINB2
+#endif
+
+#if defined(__AVR_AT90Tiny2313__) | defined(__AVR_ATtiny2313__)
+    #define DDR_USI             DDRB
+    #define PORT_USI            PORTB
+    #define PIN_USI             PINB
+    #define PORT_USI_SDA        PORTB5
+    #define PORT_USI_SCL        PORTB7
+    #define PIN_USI_SDA         PINB5
+    #define PIN_USI_SCL         PINB7
+#endif
+
+#if defined(__AVR_ATtiny84__) | defined(__AVR_ATtiny84A__)
+#define DDR_USI             DDRA
+#define PORT_USI            PORTA
+#define PIN_USI             PINA
+#define PORT_USI_SDA        PORTA6
+#define PORT_USI_SCL        PORTA4
+#define PIN_USI_SDA         PINA6
+#define PIN_USI_SCL         PINA4
+#endif
+
+
+//****************** ATMEGA TWI without USI
+#define TWI_BUFFER_SIZE 4   // Set this to the largest message size that will be sent including address byte.
+#define TWI_TWBR         0x4C; //  0x0C         // TWI Bit rate Register setting.
// Se Application note for detailed
// information on setting this value.

+
+
+
+#define ACK (1<<TWI_NACK_BIT )
+#define NO_ACK 0
+
+
+
+#if  defined(__AVR_ATmega328PB__)
+#undef ACK
+#define ACK  (1<<TWEA)
+
+#define TWBR TWBR0
+#define TWSR TWSR0
+#define TWCR TWCR0
+#define TWDR TWDR0
+#define TW_STATUS_MASK		(_BV(TWS7)|_BV(TWS6)|_BV(TWS5)|_BV(TWS4)|_BV(TWS3))
+#define TW_STATUS		(TWSR_R & TW_STATUS_MASK)
+
+#endif
+
+#if defined(__AVR_ATmega328P__)
+#undef ACK
+#define ACK  (1<<TWEA)
+
+#define TW_STATUS_MASK		(_BV(TWS7)|_BV(TWS6)|_BV(TWS5)|_BV(TWS4)|_BV(TWS3))
+#define TW_STATUS		(TWSR_R & TW_STATUS_MASK)
+
+
+#endif
+
+// General defines
+#define TRUE  1
+#define FALSE 0
+
+
+//********** Prototypes **********//
+
+void TWI_Master_Initialise( void );
+
+unsigned char I2c_WriteByte(unsigned char msg);
+unsigned char I2c_ReadByte(unsigned char ack_mode);
+void I2c_StartCondition(void);
+void I2c_StopCondition(void);
+
+#endif
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