X-Git-Url: http://git.smho.de/gw/?p=owSlave2.git;a=blobdiff_plain;f=common%2FOWRomFunctionsDual.s;h=d4d13d56a8a28a06baf83831410334c2146edc4b;hp=3c2d15246ab8b5c435b795650e596f89b644bb11;hb=HEAD;hpb=22b81b6c288ca56f58d064627c310e437f9453a4

diff --git a/common/OWRomFunctionsDual.s b/common/OWRomFunctionsDual.s
index 3c2d152..d4d13d5 100644
--- a/common/OWRomFunctionsDual.s
+++ b/common/OWRomFunctionsDual.s
@@ -105,7 +105,7 @@
 	cljmp 0x85,hrc_fw_configinfo2
 .endm
 
-#ifdef _CHANGEABLE_ID_
+//#ifdef _CHANGEABLE_ID_ //--> ID vom EEPROM lesen auch wenn sie sich nicht ändern laesst
 ; lesen der ID aus dem EEPROM beim Start
 read_EEPROM_ID1:  
 	ldi r_temp2,lo8(E2END)
@@ -139,7 +139,7 @@ read_EEPROM_ID_loop:
 	brne read_EEPROM_ID_loop
 read_EEPROM_ID_end:
 	ret
-#endif
+//#endif
 
 
 
@@ -187,11 +187,7 @@ hrc_jmp_flasher:
 	lds r_temp,flashmarker
 	cpi r_temp,2
 	brne hrc_jmp_flasher_inc
-	ldi r_temp,0xC0
-	push r_temp
-	ldi r_temp,0x0E
-	push r_temp
-	ret ; Direkter Sprung zum Bootloader
+	JMP_FLASHER
 hrc_jmp_flasher_inc:
 	inc r_temp
 	sts flashmarker,r_temp
@@ -213,13 +209,13 @@ hrc_set_searchrom:
 	rjmp h_searchrom_next_bit
 
 hrc_start_read_command: ;Skip rom und Matchrom ok...
+	CRCInit1
 	lds r_temp,srbyte
 	cpi r_temp,1
 	breq hrc_start_read_command1
 	cpi r_temp,2
 	breq hrc_start_read_command2
 	rjmp handle_end_sleep
-	CRCInit1
 hrc_start_read_command1:
 	ldi r_mode,OW_READ_COMMAND1
 	rjmp handle_end
@@ -241,17 +237,24 @@ hrc_set_alarm_search:
 	rjmp handle_end_sleep
 
 hrc_fw_configinfo1:
+#ifdef _NO_CONFIGBYTES_
+	rjmp handle_end_sleep
+#else
 	ldi r_mode,OW_FWCONFIGINFO1
 	ldi r_sendflag,1
 	CRCInit2
 	rjmp h_fwconfiginfo1
+#endif
 
 hrc_fw_configinfo2:
+#ifdef _NO_CONFIGBYTES_
+	rjmp handle_end_sleep
+#else
 	ldi r_mode,OW_FWCONFIGINFO2
 	ldi r_sendflag,1
 	CRCInit2
 	rjmp h_fwconfiginfo2
-
+#endif
 
 ;---------------------------------------------------
 ;   MATCH ROM
@@ -395,15 +398,31 @@ h_searchromr:  ; stelle um auf empfangen
 ;---------------------------------------------------
 
 h_fwconfiginfo1:
+#ifdef _NO_CONFIGBYTES_
+h_fwconfiginfo2:
+	rjmp handle_end_sleep
+#else
 	configZ config_info1,r_bytep
 	rjmp h_fwconfiginfo_go
 h_fwconfiginfo2:
 	configZ config_info2,r_bytep
+/*#ifdef _CRC16_
+	cpi  r_bytep,24
+	breq h_fwconfiginfo_crc
+	cpi  r_bytep,26
+	breq h_fwconfiginfo_all
+//h_fwconfiginfo_end:
+	//configZ config_info1,r_bytep  //crc16 wird in config_info1 gespeichert, auch bei config_info2 
+	configZ config_info2,r_bytep
+	ld   r_rwbyte,Z
+	rjmp handle_end_inc
+#endif
+*/
 
 h_fwconfiginfo_go:
 	cpi  r_bytep,24
 	breq h_fwconfiginfo_crc
-#ifdef _CRC8_
+#if defined(_CRC8_)  || defined( _CRC8_16_) 
 	cpi  r_bytep,25
 	breq h_fwconfiginfo_all
 #elif defined _CRC16_
@@ -414,8 +433,10 @@ h_fwconfiginfo_go:
 	breq h_fwconfiginfo_all
 #warning No CRC known code implemented
 #endif
+
 h_fwconfiginfo_end:
 	//configZ config_info1,r_bytep  //crc16 wird in config_info1 gespeichert, auch bei config_info2 
+	//configZ config_info1,r_bytep
 	ld   r_rwbyte,Z
 	rjmp handle_end_inc
 h_fwconfiginfo_crc:
@@ -429,11 +450,15 @@ h_fwconfiginfo_crc:
 	lds r_temp,crc+1
 	com r_temp
 	sts config_info1+25,r_temp
-	rjmp h_fwconfiginfo_end
+	ldi r_mode,OW_FWCONFIGINFO1  //auch CRC vom Dev 2 wird in Configinfo 1 geschrieben also da weiter machen
+	configZ config_info1,r_bytep
+	ld   r_rwbyte,Z
+	rjmp handle_end_inc
+
 #endif
 h_fwconfiginfo_all:
 	rjmp handle_end_sleep
-
+#endif
 
 ;---------------------------------------------------
 ;   CHANGE ROM FUNCTIONS
@@ -554,32 +579,11 @@ spause:
 .global OWINIT
 OWINIT:
 	
-#ifndef _DIS_FLASH_
 ; check for bootloader jumper
 	;vor allen anderen Registerconfigs
 	push r_temp
-
-	ldi r_temp,(1<<PUD) ;enable pullup 
-	out _SFR_IO_ADDR(MCUCR) ,r_temp
-	sbi _SFR_IO_ADDR(PORTA),PINA5 ;internal pullup on PINA5
-	sbi _SFR_IO_ADDR(PORTA),PINA4 ;internal pullup on PINA4
-	rcall spause
-	sbis _SFR_IO_ADDR(PINA),PINA5
-	rjmp owinit_botest_end  ;PinA5 nicht auf 1
-  	sbis _SFR_IO_ADDR(PINA),PINA4
-	rjmp owinit_botest_end ;PinA4 nicht auf 1
-	cbi _SFR_IO_ADDR(PORTA),PINA4 
-	sbi _SFR_IO_ADDR(DDRA),PINA4  ;PINA4 AUSGANG und 0
-	rcall spause
-	sbic _SFR_IO_ADDR(PINA),PINA5 
-	rjmp owinit_botest_end ;PINA5 nicht 0.... nicht verbunden
-	cbi _SFR_IO_ADDR(DDRA),PINA4
-	ldi r_temp,0xC0
-	push r_temp
-	ldi r_temp,0x0E
-	push r_temp
-	ret ; Direkter Sprung zum Bootloader*/
-owinit_botest_end:
+#ifndef _DIS_FLASH_
+	CHECK_BOOTLOADER_PIN 
 #endif
 	HW_INIT  //Microcontroller specific
 	CHIP_INIT //1-Wire device specific
@@ -591,10 +595,10 @@ init_idtable:
 	push r_rwbyte
 	push r_idn1
 	push r_idn2
-#ifdef _CHANGEABLE_ID_
+//#ifdef _CHANGEABLE_ID_
 	rcall read_EEPROM_ID1
 	rcall read_EEPROM_ID2
-#endif
+//#endif
 	ldi r_bytep,8
 	ldi r_temp,0
 	ldi  zl,lo8(idtable)
@@ -635,6 +639,7 @@ owinit_odgen2:
 	dec r_bytep
 	brne owinit_odgen1
 	;copy ids in config bytes
+#ifndef _NO_CONFIGBYTES_
 	ldi  xl,lo8(owid1)
 	ldi  xh,hi8(owid1)
 	ldi	 yl,lo8(config_info2+17)
@@ -655,7 +660,7 @@ owinit_cpconfig2:
 	st Y+,r_rwbyte
 	dec r_temp
 	brne owinit_cpconfig2
-
+#endif
 
 	ldi r_temp,0
 	sts mode,r_temp