2 // Copyright (c) 2017, Tobias Mueller tm(at)tm3d.de
3 // All rights reserved.
5 // Redistribution and use in source and binary forms, with or without
6 // modification, are permitted provided that the following conditions are
9 // * Redistributions of source code must retain the above copyright
10 // notice, this list of conditions and the following disclaimer.
11 // * Redistributions in binary form must reproduce the above copyright
12 // notice, this list of conditions and the following disclaimer in the
13 // documentation and/or other materials provided with the
15 // * All advertising materials mentioning features or use of this
16 // software must display the following acknowledgement: This product
17 // includes software developed by tm3d.de and its contributors.
18 // * Neither the name of tm3d.de nor the names of its contributors may
19 // be used to endorse or promote products derived from this software
20 // without specific prior written permission.
22 // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
23 // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
24 // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
25 // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
26 // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
27 // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
28 // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
29 // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
30 // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
32 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34 #define F_CPU 8000000UL
36 #include <avr/interrupt.h>
37 #include <util/delay.h>
39 #include <avr/sleep.h>
40 #include <avr/pgmspace.h>
41 #include "../common/I2C/USI_TWI_Master.h"
42 #include "../common/I2C/IAQCORE.h"
45 extern void EXTERN_SLEEP();
47 uint8_t owid[8]={0x20, 0xA2, 0xD9, 0x84, 0x00, 0x16, 0x02, 0x5D};/**/
48 uint8_t config_info[26]={0x06,13,0x06,13,0x06,13,0x06,13,0x02,20,20,20,20,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00};
51 #error "Variable not correct"
55 extern uint8_t gcontrol;
56 extern uint8_t reset_indicator;
57 extern uint8_t alarmflag;
61 volatile uint8_t bytes[0x20];
101 volatile pack_t pack;
105 IAQCORE_Data_t IAQCORE_Data;
132 MCUCR &=~(1<<PUD); //All Pins Pullup...
134 PORTA&=~((1<<PINA0)|(1<<PINA1)|(1<<PINA2)|(1<<PINA3));
135 ADCSRA=(1<<ADEN)|(1<ADPS0)|(1<<ADPS2);
140 USI_TWI_Master_Initialise();
150 readIAQCORE(&IAQCORE_Data);
154 for(uint8_t i=0;i<4;i++){
155 if (pack.convc1&bb1) {
156 if (pack.convc2&(bb)) {pack.bytes[i*2]=0;pack.bytes[i*2+1]=0;}
158 if (pack.convc2&(bb)) {pack.bytes[i*2]=0xFF;pack.bytes[i*2+1]=0xFF;}
165 cli();pack.A=IAQCORE_Data.CO2;sei();
167 if (pack.CSA2&0x08) //AEH
168 if (pack.bytes[1]>pack.HA) {alarmflag=1;pack.CSA2|=0x20;}
169 if (pack.CSA2&0x04) //AEL
170 if (pack.bytes[1]<pack.LA) {alarmflag=1;pack.CSA2|=0x10;}
174 cli();pack.B=IAQCORE_Data.TVOC;sei();
175 if (pack.CSB2&0x08) //AEH
176 if (pack.bytes[1]>pack.HB) {alarmflag=1;pack.CSB2|=0x20;}
177 if (pack.CSB2&0x04) //AEL
178 if (pack.bytes[1]<pack.LB) {alarmflag=1;pack.CSB2|=0x10;}
182 cli();pack.C=IAQCORE_Data.resistance/1000;sei();
183 if (pack.CSC2&0x08) //AEH
184 if (pack.bytes[1]>pack.HC) {alarmflag=1;pack.CSC2|=0x20;}
185 if (pack.CSC2&0x04) //AEL
186 if (pack.bytes[1]<pack.LC) {alarmflag=1;pack.CSC2|=0x10;}
189 cli();pack.D=IAQCORE_Data.state;sei();
190 if (pack.CSD2&0x08) //AEH
191 if (pack.bytes[1]>pack.HD) {alarmflag=1;pack.CSD2|=0x20;}
192 if (pack.CSD2&0x04) //AEL
193 if (pack.bytes[1]<pack.LD) {alarmflag=1;pack.CSD2|=0x10;}
197 //PORTB&=~(1<<PINB1);
201 for(uint8_t i=0;i<4;i++) {
202 if (pack.bytes[8+i*2]&0x80) { //Chanel as output
203 if (pack.bytes[8+i*2]&0x40) {
214 #if defined(__AVR_ATtiny25__)||defined(__AVR_ATtiny45__) || defined(__AVR_ATtiny85__)
215 if (((TIMSK & (1<<TOIE0))==0)&& (mode==0))
217 #if defined(__AVR_ATtiny24__)||defined(__AVR_ATtiny44__) || defined(__AVR_ATtiny84__) ||defined(__AVR_ATtiny24A__)||defined(__AVR_ATtiny44A__) || defined(__AVR_ATtiny84A__)
218 if (((TIMSK0 & (1<<TOIE0))==0)&& (mode==0))
222 MCUCR|=(1<<SE)|(1<<SM1);