1 // Copyright (c) 2015, Tobias Mueller tm(at)tm3d.de
2 // All rights reserved.
4 // Redistribution and use in source and binary forms, with or without
5 // modification, are permitted provided that the following conditions are
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16 // includes software developed by tm3d.de and its contributors.
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39 .macro cljmp val,addr; Weiter sprung, wenn das ziel zu weit entfernt fuer brxx
46 .macro cset val,mod ;Nur der Mode wird gesetzt. Abkuerzung da oft nur das noch bleibt
58 #define OW_READ_ROM_COMMAND 1
60 #define OW_SEARCHROMS 3 ;next send two bit
61 #define OW_SEARCHROMR 4 ; next resive master answer
62 #define OW_READ_COMMAND1 5
63 #define OW_READ_COMMAND2 6
66 #ifdef _CHANGEABLE_ID_
67 #define OW_WRITE_NEWID 7
68 #define OW_READ_NEWID 8
69 #define OW_SET_NEWID 9
70 #define OW_FIRST_COMMAND 10
74 .macro CHANGE_ID_COMMANDS
75 cset 0x75,OW_WRITE_NEWID
76 cljmp 0xA7,hrc_set_readid
77 cljmp 0x79,hrc_set_setid
82 #define OW_FIRST_COMMAND 7
86 ; test auf run flasher command 0x88 in h_readcommand
91 1: ldi r_temp,0 ;Anderes Kommando flashmarker zuruecksetzen...
92 sts flashmarker,r_temp
98 #ifdef _CHANGEABLE_ID_
99 ; lesen der ID aus dem EEPROM beim Start
101 ldi r_temp2,lo8(E2END)
104 out _SFR_IO_ADDR(EEARH), zh
108 rjmp read_EEPROM_ID_loop
110 ldi r_temp2,lo8(E2END)
113 out _SFR_IO_ADDR(EEARH), zh
118 sbic _SFR_IO_ADDR(EECR), EEPE
119 rjmp read_EEPROM_ID_loop
120 out _SFR_IO_ADDR(EEARL),r_temp2
121 sbi _SFR_IO_ADDR(EECR), EERE
122 in r_rwbyte,_SFR_IO_ADDR(EEDR)
124 breq read_EEPROM_ID_end
129 brne read_EEPROM_ID_loop
141 rjmp handle_end_no_bcount // sleep eventuell reset, nichts tun und auf Timeout warten
142 rjmp h_readromcommand
148 #ifdef _CHANGEABLE_ID_
159 cjmp 0x55,hrc_set_matchrom
160 cjmp 0xF0,hrc_set_searchrom
161 cjmp 0xEC,hrc_set_alarm_search
163 rjmp handle_end_sleep
168 lds r_temp,flashmarker
170 brne hrc_jmp_flasher_inc
175 ret ; Direkter Sprung zum Bootloader
178 sts flashmarker,r_temp
179 rjmp handle_end_sleep
184 sts srbyte,r_temp ; Beide geraete nehmen an searchrom teil
185 ldi r_mode,OW_MATCHROM
192 sts srbyte,r_temp ; Beide geraete nehmen an searchrom teil
193 configZ idtable,r_bytep
194 rjmp h_searchrom_next_bit
196 hrc_start_read_command: ;Skip rom und Matchrom ok...
199 breq hrc_start_read_command1
201 breq hrc_start_read_command2
202 rjmp handle_end_sleep
204 hrc_start_read_command1:
205 ldi r_mode,OW_READ_COMMAND1
207 hrc_start_read_command2:
208 ldi r_mode,OW_READ_COMMAND2
212 hrc_set_alarm_search:
215 brne hrc_set_searchrom ;alarm flag nicht 0 also gehe zu searchrom
217 rjmp handle_end_sleep
219 ;---------------------------------------------------
221 ;---------------------------------------------------
226 sbrs r_bcount,0 ;ueberspringe wenn bit 1 =0 also geraet 1 nich mehr im rennen
228 configZ owid1,r_bytep
232 cbr r_bcount,1 ; loesche geraet
233 breq h_matchrom_sleep
235 configZ owid2,r_bytep
239 cbr r_bcount,2 ; loesche geraet
240 breq h_matchrom_sleep
245 breq hrc_start_read_command ;Starten von Read Command
250 rjmp handle_end_sleep
253 ;---------------------------------------------------
255 ;---------------------------------------------------
258 h_searchrom_next_bit: ;Setup next Bit of ID
260 lds r_temp,srbyte ;srbyte ist ein zeiger auf die bits fuer ein bit im Table
261 h_searchrom_next_bit_l2:
263 breq h_searchrom_next_bit_l1
267 rjmp h_searchrom_next_bit_l2
268 h_searchrom_next_bit_l1:
270 rol r_rwbyte ; negiertes bit in rwbyte
272 rol r_rwbyte ; bit in rwbyte
274 ldi r_bcount,0x40 ; zwei bits sensden dann zu Searchromr
275 ldi r_mode,OW_SEARCHROMR
276 rjmp handle_end_no_bcount
280 h_searchroms: ; Modus Send zwei bit
281 configZ idtable,r_bytep
285 breq h_searchroms_idd
287 breq h_searchroms_id1
289 breq h_searchroms_id2
290 rjmp handle_end_sleep ; zur Sicherheit.....
293 breq h_searchroms_idd_zero
295 sbrc r_temp2,0 ;springe wenn nicht beide bits 0 (id 1 negiert und id 2 negiert)
296 rjmp handle_end_sleep ;
297 sbrc r_temp2,4 ;id1 set? then skip
298 cbr r_temp,1 ; loesche bit 1 in srbyte
299 sbrc r_temp2,2 ; springe wenn id 2 gesetzt ist
300 cbr r_temp,2 ; loesche bit 2 in srbyte
302 rjmp h_searchroms_idX_end
303 h_searchroms_idd_zero:
304 sbrc r_temp2,1 ;springe wenn nicht beide 1 (id 1 und id 2 )
305 rjmp handle_end_sleep ;beide 1 gehe schlafen
306 sbrs r_temp2,4 ;id1 0? then skip
307 cbr r_temp,1 ; loesche bit 1 in srbyte
308 sbrs r_temp2,2 ; springe wenn id 2 null ist
309 cbr r_temp,2 ; loesche bit 2 in srbyte
311 rjmp h_searchroms_idX_end
314 breq h_searchroms_id1_zero
316 sbrs r_temp2,5 ;id1 set? then skip
317 rjmp handle_end_sleep ;
318 rjmp h_searchroms_idX_end
319 h_searchroms_id1_zero:
320 sbrs r_temp2,4 ;id1 set? then skip
321 rjmp handle_end_sleep ;
322 rjmp h_searchroms_idX_end
325 breq h_searchroms_id2_zero
327 sbrs r_temp2,3 ;id1 set? then skip
328 rjmp handle_end_sleep ;
329 rjmp h_searchroms_idX_end
330 h_searchroms_id2_zero:
331 sbrs r_temp2,2 ;id1 set? then skip
332 rjmp handle_end_sleep ;
333 rjmp h_searchroms_idX_end
334 h_searchroms_idX_end:
337 brne h_searchroms_idX_end1
338 rjmp handle_end_sleep
339 h_searchroms_idX_end1:
342 breq h_searchrom_end_ok ;unterschied nur das letzt bit wird wohl nie vorkommen
343 rjmp h_searchrom_next_bit
347 rjmp hrc_start_read_command
349 h_searchromr: ; stelle um auf empfangen
351 ldi r_mode,OW_SEARCHROMS
352 ldi r_bcount,0 ;gehe nach einem bit zu SEARCHROMS
353 rjmp handle_end_no_bcount
357 ;---------------------------------------------------
358 ; CHANGE ROM FUNCTIONS
359 ;---------------------------------------------------
362 #ifdef _CHANGEABLE_ID_
365 configZ newid,r_bytep
371 rjmp handle_end_sleep
375 ldi r_mode,OW_READ_NEWID
380 configZ newid,r_bytep
385 rjmp handle_end_sleep
388 ldi r_mode,OW_SET_NEWID
389 ;ldi r_bytep,1 ;start to write in 2
390 rjmp handle_end_inc ;set r_bytep to 1!!!
397 configZ owid1,r_bytep
400 configZ owid2,r_bytep
404 brne h_setid_bad_code_all
411 rjmp h_setid_bad_code_all ;sollte eigentlich nicht passieren
419 ldi r_temp2,lo8(E2END)
425 ;ldi r_temp,0 ;kommt nicht vor das ein E2ROM genau n*256+(0 bis 7) byte gross ist
427 out _SFR_IO_ADDR(EEARH),zh
431 h_setid_EEPROM_write:
432 sbic _SFR_IO_ADDR(EECR), EEPE
433 rjmp h_setid_EEPROM_write
434 ldi r_temp, (0<<EEPM1)|(0<<EEPM0)
435 out _SFR_IO_ADDR(EECR), r_temp
436 ;nur adresse L schreiben H bleibt aus oben genannten grund gleich.
437 out _SFR_IO_ADDR(EEARL),r_temp2
439 out _SFR_IO_ADDR(EEDR), r_rwbyte
440 sbi _SFR_IO_ADDR(EECR), EEMPE
441 sbi _SFR_IO_ADDR(EECR), EEPE
445 brne h_setid_EEPROM_write
446 //rcall read_EEPROM_ID1
447 //rcall read_EEPROM_ID2
465 h_setid_bad_code_all:
466 rjmp handle_end_sleep
484 ; check for bootloader jumper
485 ;vor allen anderen Registerconfigs
487 ldi r_temp,(1<<PUD) ;enable pullup
488 out _SFR_IO_ADDR(MCUCR) ,r_temp
489 sbi _SFR_IO_ADDR(PORTA),PINA5 ;internal pullup on PINA5
490 sbi _SFR_IO_ADDR(PORTA),PINA4 ;internal pullup on PINA4
492 sbis _SFR_IO_ADDR(PINA),PINA5
493 rjmp owinit_botest_end ;PinA5 nicht auf 1
494 sbis _SFR_IO_ADDR(PINA),PINA4
495 rjmp owinit_botest_end ;PinA4 nicht auf 1
496 cbi _SFR_IO_ADDR(PORTA),PINA4
497 sbi _SFR_IO_ADDR(DDRA),PINA4 ;PINA4 AUSGANG und 0
499 sbic _SFR_IO_ADDR(PINA),PINA5
500 rjmp owinit_botest_end ;PINA5 nicht 0.... nicht verbunden
501 cbi _SFR_IO_ADDR(DDRA),PINA4
506 ret ; Direkter Sprung zum Bootloader*/
509 HW_INIT //Microcontroller specific
510 CHIP_INIT //1-Wire device specific
511 #ifdef _CHANGEABLE_ID_
513 rcall read_EEPROM_ID1
514 rcall read_EEPROM_ID2
539 rol r_mode ;6. Bit id1
541 rol r_mode ; 5. Bit id1negiert
543 rol r_mode ;;4. Bit id2
545 rol r_mode ;3. Bit id2 negiert
547 rol r_mode ;zweites bit id1 und id2
549 rol r_mode ;erstes bit id1 negiert und id2 negiert