2 // Copyright (c) 2017, Tobias Mueller tm(at)tm3d.de
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3 // All rights reserved.
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5 // Redistribution and use in source and binary forms, with or without
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6 // modification, are permitted provided that the following conditions are
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9 // * Redistributions of source code must retain the above copyright
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10 // notice, this list of conditions and the following disclaimer.
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11 // * Redistributions in binary form must reproduce the above copyright
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12 // notice, this list of conditions and the following disclaimer in the
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13 // documentation and/or other materials provided with the
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15 // * All advertising materials mentioning features or use of this
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16 // software must display the following acknowledgement: This product
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17 // includes software developed by tm3d.de and its contributors.
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18 // * Neither the name of tm3d.de nor the names of its contributors may
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19 // be used to endorse or promote products derived from this software
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20 // without specific prior written permission.
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22 // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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23 // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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24 // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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25 // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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26 // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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27 // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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28 // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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29 // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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30 // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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31 // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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32 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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34 #define F_CPU 8000000UL
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36 #include <avr/interrupt.h>
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37 #include <util/delay.h>
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38 #include <avr/wdt.h>
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39 #include <avr/sleep.h>
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40 #include <avr/pgmspace.h>
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41 #include "../common/I2C/USI_TWI_Master.h"
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43 extern void OWINIT();
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44 extern void EXTERN_SLEEP();
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46 uint8_t owid[8]={0x20, 0xA2, 0xD9, 0x84, 0x00, 0x16, 0x02, 0x5D};/**/
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47 uint8_t config_info[26]={0x06,0x09,0x06,0x09,0x06,0x09,0x06,0x09,0x02,20,20,20,20,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00};
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50 #error "Variable not correct"
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53 extern uint8_t mode;
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54 extern uint8_t gcontrol;
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55 extern uint8_t reset_indicator;
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56 extern uint8_t alarmflag;
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60 volatile uint8_t bytes[0x20];
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100 volatile pack_t pack;
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103 uint8_t checkMAX44008(uint8_t nr) {
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104 volatile uint8_t b1;
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107 I2c_StartCondition();
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108 I2c_WriteByte(0b10000000|nr);
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109 I2c_WriteByte(0x00);
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110 I2c_StartCondition();
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111 I2c_WriteByte (0b10000001|nr);
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112 b1 =I2c_ReadByte(NO_ACK);
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113 I2c_StopCondition();
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148 MCUCR &=~(1<<PUD); //All Pins Pullup...
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150 //PORTA&=~((1<<PINA0)|(1<<PINA1)|(1<<PINA2)|(1<<PINA3));
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152 ADCSRA=(1<<ADEN)|(1<ADPS0)|(1<<ADPS2);
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157 ADCSRB|=(1<<ADLAR);
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158 USI_TWI_Master_Initialise();
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165 //DDRB|=(1<<PINB1);
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171 //PORTB|=(1<<PINB1);
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174 for(uint8_t i=0;i<4;i++){
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175 if (pack.convc1&bb1) {
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176 if (pack.convc2&(bb)) {pack.bytes[i*2]=0;pack.bytes[i*2+1]=0;}
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178 if (pack.convc2&(bb)) {pack.bytes[i*2]=0xFF;pack.bytes[i*2+1]=0xFF;}
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184 if (pack.convc1&1) {
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185 if (pack.CSA2&0x01) ADMUX=0; else ADMUX=0x80;
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188 while ((ADCSRA&(1<<ADSC)));
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189 cli();pack.A=ADC;sei();
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190 pack.A= checkMAX44008(0);
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192 if (pack.CSA2&0x08) //AEH
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193 if (pack.bytes[1]>pack.HA) {alarmflag=1;pack.CSA2|=0x20;}
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194 if (pack.CSA2&0x04) //AEL
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195 if (pack.bytes[1]<pack.LA) {alarmflag=1;pack.CSA2|=0x10;}
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198 if (pack.convc1&2) {
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199 if (pack.CSB2&0x01) ADMUX=1; else ADMUX=0x81;
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202 while ((ADCSRA&(1<<ADSC)));
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203 cli();pack.B=ADC;sei();
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204 pack.B= checkMAX44008(1);
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205 if (pack.CSB2&0x08) //AEH
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206 if (pack.bytes[1]>pack.HB) {alarmflag=1;pack.CSB2|=0x20;}
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207 if (pack.CSB2&0x04) //AEL
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208 if (pack.bytes[1]<pack.LB) {alarmflag=1;pack.CSB2|=0x10;}
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211 if (pack.convc1&4) {
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212 if (pack.CSC2&0x01) ADMUX=2; else ADMUX=0x82;
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215 while ((ADCSRA&(1<<ADSC)));
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216 cli();pack.C=ADC;sei();
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217 if (pack.CSC2&0x08) //AEH
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218 if (pack.bytes[1]>pack.HC) {alarmflag=1;pack.CSC2|=0x20;}
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219 if (pack.CSC2&0x04) //AEL
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220 if (pack.bytes[1]<pack.LC) {alarmflag=1;pack.CSC2|=0x10;}
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222 if (pack.convc1&8) {
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223 if (pack.CSD2&0x01) ADMUX=3; else ADMUX=0x83;
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226 while ((ADCSRA&(1<<ADSC)));
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227 cli();pack.D=ADC;sei();
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228 if (pack.CSD2&0x08) //AEH
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229 if (pack.bytes[1]>pack.HD) {alarmflag=1;pack.CSD2|=0x20;}
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230 if (pack.CSD2&0x04) //AEL
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231 if (pack.bytes[1]<pack.LD) {alarmflag=1;pack.CSD2|=0x10;}
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235 //PORTB&=~(1<<PINB1);
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239 for(uint8_t i=0;i<4;i++) {
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240 if (pack.bytes[8+i*2]&0x80) { //Chanel as output
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241 if (pack.bytes[8+i*2]&0x40) {
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252 #if defined(__AVR_ATtiny25__)||defined(__AVR_ATtiny45__) || defined(__AVR_ATtiny85__)
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253 if (((TIMSK & (1<<TOIE0))==0)&& (mode==0))
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255 #if defined(__AVR_ATtiny24__)||defined(__AVR_ATtiny44__) || defined(__AVR_ATtiny84__) ||defined(__AVR_ATtiny24A__)||defined(__AVR_ATtiny44A__) || defined(__AVR_ATtiny84A__)
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256 if (((TIMSK0 & (1<<TOIE0))==0)&& (mode==0))
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260 MCUCR|=(1<<SE)|(1<<SM1);
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261 MCUCR&=~(1<<ISC01);
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