1 // Copyright (c) 2017, Tobias Mueller tm(at)tm3d.de
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2 // All rights reserved.
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4 // Redistribution and use in source and binary forms, with or without
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5 // modification, are permitted provided that the following conditions are
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8 // * Redistributions of source code must retain the above copyright
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9 // notice, this list of conditions and the following disclaimer.
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10 // * Redistributions in binary form must reproduce the above copyright
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11 // notice, this list of conditions and the following disclaimer in the
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12 // documentation and/or other materials provided with the
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14 // * All advertising materials mentioning features or use of this
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15 // software must display the following acknowledgement: This product
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16 // includes software developed by tm3d.de and its contributors.
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17 // * Neither the name of tm3d.de nor the names of its contributors may
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18 // be used to endorse or promote products derived from this software
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19 // without specific prior written permission.
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21 // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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22 // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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23 // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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24 // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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25 // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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26 // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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27 // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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28 // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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29 // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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30 // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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31 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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35 .macro cjmp val,addr
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39 .macro cljmp val,addr; Weiter sprung, wenn das ziel zu weit entfernt fuer brxx
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46 .macro cset val,mod ;Nur der Mode wird gesetzt. Abkuerzung da oft nur das noch bleibt
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58 #define OW_READ_ROM_COMMAND 1
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59 #define OW_MATCHROM 2
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60 #define OW_SEARCHROMS 3 ;next send two bit
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61 #define OW_SEARCHROMR 4 ; next resive master answer
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62 #define OW_READROM 5
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63 #define OW_READ_COMMAND 6
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64 #define OW_FWCONFIGINFO 7
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67 #ifdef _CHANGEABLE_ID_
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68 #define OW_WRITE_NEWID 8
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69 #define OW_READ_NEWID 9
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70 #define OW_SET_NEWID 10
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71 #define OW_FIRST_COMMAND 11
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75 .macro CHANGE_ID_COMMANDS
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76 cset 0x75,OW_WRITE_NEWID
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77 cljmp 0xA7,hrc_set_readid
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78 cljmp 0x79,hrc_set_setid
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83 #define OW_FIRST_COMMAND 8
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87 ; test auf run flasher command 0x88 in h_readcommand
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88 .macro FLASH_COMMANDS
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91 rjmp hrc_jmp_flasher
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92 1: ldi r_temp,0 ;Anderes Kommando flashmarker zuruecksetzen...
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93 sts flashmarker,r_temp
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97 .macro FW_CONFIG_INFO
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98 cljmp 0x85,hrc_fw_configinfo
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102 #ifdef _CHANGEABLE_ID_
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103 ; lesen der ID aus dem EEPROM beim Start
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106 push r_rwbyte//r_temp2 and Z is not in gnu C save area
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107 ldi r_temp2,lo8(E2END)
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110 out _SFR_IO_ADDR(EEARH), zh
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114 read_EEPROM_ID_loop:
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115 sbic _SFR_IO_ADDR(EECR), EEPE
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116 rjmp read_EEPROM_ID_loop
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117 out _SFR_IO_ADDR(EEARL),r_temp2
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118 sbi _SFR_IO_ADDR(EECR), EERE
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119 in r_rwbyte,_SFR_IO_ADDR(EEDR)
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121 breq read_EEPROM_ID_end
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126 brne read_EEPROM_ID_loop
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127 read_EEPROM_ID_end:
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139 rjmp handle_end_no_bcount // sleep eventuell reset, nichts tun und auf Timeout warten
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140 rjmp h_readromcommand
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145 rjmp h_readcommand
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146 rjmp h_fwconfiginfo
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147 #ifdef _CHANGEABLE_ID_
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158 cset 0x55,OW_MATCHROM
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159 cjmp 0xF0,hrc_set_searchrom
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160 cjmp 0xCC,hrc_start_read_command ;skip rom
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161 cjmp 0x33,hrc_set_read_rom
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162 cjmp 0xEC,hrc_set_alarm_search
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164 rjmp handle_end_sleep
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166 #ifndef _DIS_FLASH_
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167 ;sprung zum flasher
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169 lds r_temp,flashmarker
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171 brne hrc_jmp_flasher_inc
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176 ret ; Direkter Sprung zum Bootloader
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177 hrc_jmp_flasher_inc:
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179 sts flashmarker,r_temp
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180 rjmp handle_end_sleep
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184 hrc_set_searchrom:
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185 lds r_rwbyte,owid ;erstes Byte lesen
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186 rjmp h_searchrom_next_bit
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190 hrc_start_read_command: ;Skip rom und Matchrom ok...
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191 ldi r_mode,OW_READ_COMMAND
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196 ldi r_mode,OW_READROM
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200 hrc_set_alarm_search:
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201 lds r_temp,alarmflag
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203 brne hrc_set_searchrom ;alarm flag nicht 0 also gehe zu searchrom
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205 rjmp handle_end_sleep
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209 ldi r_mode,OW_FWCONFIGINFO
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212 rjmp h_fwconfiginfo
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215 ;---------------------------------------------------
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217 ;---------------------------------------------------
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221 configZ owid,r_bytep
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225 rjmp handle_end_sleep
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229 breq hrc_start_read_command ;Starten von Read Command
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230 rjmp handle_end_inc
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234 ;---------------------------------------------------
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236 ;---------------------------------------------------
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239 h_searchrom_next_bit: ;Setup next Bit of ID
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240 sts srbyte,r_rwbyte ;erstes Byte speichern von der Aufrufenden Ebene
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241 mov r_temp2,r_rwbyte
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242 com r_rwbyte ; negieren
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243 ror r_temp2 ; erstes unnegiertes bit in Carry
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244 rol r_rwbyte ;und dann als erstes bit in r_rwbyte
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246 ldi r_bcount,0x40 ; zwei bits sensden dann zu Searchromr
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247 ldi r_mode,OW_SEARCHROMR
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248 rjmp handle_end_no_bcount
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252 h_searchroms: ; Modus Send zwei bit
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254 sbrc r_rwbyte,7 ; bit gesetz (1 empfangen)
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256 lds r_bcount,srbyte ;r_bcount wird am ende gesetzt
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257 eor r_temp,r_bcount
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259 rjmp h_searchroms_next ; Vergleich des letzen gelesenen bits mit der id
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264 rjmp handle_end_sleep
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265 h_searchroms_next: ; Setup next bit
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266 inc r_bytep ; zaehler der Bits erhoehen
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267 sbrc r_bytep,6 ; 64 bit erreicht
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268 rjmp h_searchrom_end_ok ;alles ok auf Command warten
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269 mov r_temp,r_bytep
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271 brne h_searchroms_next_bit ; bit zwischen 0 und 8
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272 mov r_bcount,r_bytep ; next Byte lesen
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277 configZ owid,r_bcount
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279 sts srbyte,r_rwbyte
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280 rjmp h_searchrom_next_bit
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282 h_searchroms_next_bit: ;next Bit lesen
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283 ;sts srbytep,r_bcount
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284 lds r_rwbyte,srbyte
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285 lsr r_rwbyte ;aktuelles byte weiterschieben r_rwbyte hier zweckefrei verwendet
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286 rjmp h_searchrom_next_bit ;algemeine routine zum vorbereiten
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287 h_searchrom_end_ok:
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289 rjmp hrc_start_read_command
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293 ldi r_mode,OW_SEARCHROMS
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295 rjmp handle_end_no_bcount
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298 ;---------------------------------------------------
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300 ;---------------------------------------------------
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305 configZ owid,r_bytep
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307 rjmp handle_end_inc
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309 rjmp handle_end_sleep
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312 ;---------------------------------------------------
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314 ;---------------------------------------------------
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318 breq h_fwconfiginfo_crc
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321 breq h_fwconfiginfo_all
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322 #elif defined _CRC16_
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324 breq h_fwconfiginfo_all
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327 breq h_fwconfiginfo_all
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328 #warning No CRC known code implemented
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330 h_fwconfiginfo_end:
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331 configZ config_info,r_bytep
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333 rjmp handle_end_inc
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334 h_fwconfiginfo_crc:
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337 rjmp handle_end_inc
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338 #elif defined _CRC16_
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341 sts config_info+24,r_temp
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344 sts config_info+25,r_temp
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345 rjmp h_fwconfiginfo_end
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347 h_fwconfiginfo_all:
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348 rjmp handle_end_sleep
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351 ;---------------------------------------------------
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352 ; CHANGE ROM FUNCTIONS
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353 ;---------------------------------------------------
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356 #ifdef _CHANGEABLE_ID_
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359 configZ newid,r_bytep
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363 rjmp handle_end_inc
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365 rjmp handle_end_sleep
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369 ldi r_mode,OW_READ_NEWID
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374 configZ newid,r_bytep
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376 rjmp handle_end_inc
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379 rjmp handle_end_sleep
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382 ldi r_mode,OW_SET_NEWID
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383 ;ldi r_bytep,1 ;start to write in 2
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384 rjmp handle_end_inc ;set r_bytep to 1!!!
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387 configZ owid,r_bytep
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390 brne h_setid_bad_code_all
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396 breq h_setid_copy_id
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397 rjmp h_setid_bad_code_all ;sollte eigentlich nicht passieren
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405 ldi r_temp2,lo8(E2END)
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409 ;ldi r_temp,0 ;kommt nicht vor das ein E2ROM genau n*256+(0 bis 7) byte gross ist
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411 out _SFR_IO_ADDR(EEARH),zh
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415 h_setid_EEPROM_write:
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416 sbic _SFR_IO_ADDR(EECR), EEPE
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417 rjmp h_setid_EEPROM_write
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418 ldi r_temp, (0<<EEPM1)|(0<<EEPM0)
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419 out _SFR_IO_ADDR(EECR), r_temp
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420 ;nur adresse L schreiben H bleibt aus oben genannten grund gleich.
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421 out _SFR_IO_ADDR(EEARL),r_temp2
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423 out _SFR_IO_ADDR(EEDR), r_rwbyte
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424 sbi _SFR_IO_ADDR(EECR), EEMPE
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425 sbi _SFR_IO_ADDR(EECR), EEPE
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429 brne h_setid_EEPROM_write
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430 rcall read_EEPROM_ID
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431 h_setid_bad_code_all:
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432 rjmp handle_end_sleep
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449 #ifndef _DIS_FLASH_
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450 ; check for bootloader jumper
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451 ;vor allen anderen Registerconfigs
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453 ldi r_temp,(1<<PUD) ;enable pullup
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454 out _SFR_IO_ADDR(MCUCR) ,r_temp
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455 sbi _SFR_IO_ADDR(PORTA),PINA5 ;internal pullup on PINA5
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456 sbi _SFR_IO_ADDR(PORTA),PINA4 ;internal pullup on PINA4
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458 sbis _SFR_IO_ADDR(PINA),PINA5
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459 rjmp owinit_botest_end ;PinA5 nicht auf 1
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460 sbis _SFR_IO_ADDR(PINA),PINA4
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461 rjmp owinit_botest_end ;PinA4 nicht auf 1
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462 cbi _SFR_IO_ADDR(PORTA),PINA4
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463 sbi _SFR_IO_ADDR(DDRA),PINA4 ;PINA4 AUSGANG und 0
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465 sbic _SFR_IO_ADDR(PINA),PINA5
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466 rjmp owinit_botest_end ;PINA5 nicht 0.... nicht verbunden
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467 cbi _SFR_IO_ADDR(DDRA),PINA4
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472 ret ; Direkter Sprung zum Bootloader*/
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475 HW_INIT //Microcontroller specific
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476 CHIP_INIT //1-Wire device specific
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477 #ifdef _CHANGEABLE_ID_
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478 rcall read_EEPROM_ID
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483 sts alarmflag,r_temp
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489 .global EXTERN_SLEEP
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494 sts mode,r_temp ;SLEEP
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495 sts gcontrol,r_temp
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496 sts sendflag,r_temp
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