1 // Copyright (c) 2017, Tobias Mueller tm(at)tm3d.de
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2 // All rights reserved.
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4 // Redistribution and use in source and binary forms, with or without
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5 // modification, are permitted provided that the following conditions are
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8 // * Redistributions of source code must retain the above copyright
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9 // notice, this list of conditions and the following disclaimer.
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10 // * Redistributions in binary form must reproduce the above copyright
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11 // notice, this list of conditions and the following disclaimer in the
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12 // documentation and/or other materials provided with the
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14 // * All advertising materials mentioning features or use of this
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15 // software must display the following acknowledgement: This product
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16 // includes software developed by tm3d.de and its contributors.
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17 // * Neither the name of tm3d.de nor the names of its contributors may
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18 // be used to endorse or promote products derived from this software
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19 // without specific prior written permission.
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21 // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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22 // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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23 // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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24 // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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25 // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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26 // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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27 // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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28 // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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29 // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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30 // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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31 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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35 .macro cjmp val,addr
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39 .macro cljmp val,addr; Weiter sprung, wenn das ziel zu weit entfernt fuer brxx
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46 .macro cset val,mod ;Nur der Mode wird gesetzt. Abkuerzung da oft nur das noch bleibt
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58 #define OW_READ_ROM_COMMAND 1
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59 #define OW_MATCHROM 2
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60 #define OW_SEARCHROMS 3 ;next send two bit
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61 #define OW_SEARCHROMR 4 ; next resive master answer
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62 #define OW_READ_COMMAND1 5
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63 #define OW_READ_COMMAND2 6
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64 #define OW_READ_COMMAND12 7 ;Skip ROM.... eigentlich nicht mit mehreren geraeten, aber bei loxone schon (CC 44)
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65 #define OW_FWCONFIGINFO1 8
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66 #define OW_FWCONFIGINFO2 9
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70 #ifdef _CHANGEABLE_ID_
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71 #define OW_WRITE_NEWID 10
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72 #define OW_READ_NEWID 11
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73 #define OW_SET_NEWID 12
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74 #define OW_FIRST_COMMAND 13
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78 .macro CHANGE_ID_COMMANDS
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79 cset 0x75,OW_WRITE_NEWID
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80 cljmp 0xA7,hrc_set_readid
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81 cljmp 0x79,hrc_set_setid
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86 #define OW_FIRST_COMMAND 10
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90 ; test auf run flasher command 0x88 in h_readcommand
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91 .macro FLASH_COMMANDS
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94 rjmp hrc_jmp_flasher
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95 1: ldi r_temp,0 ;Anderes Kommando flashmarker zuruecksetzen...
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96 sts flashmarker,r_temp
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101 .macro FW_CONFIG_INFO1
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102 cljmp 0x85,hrc_fw_configinfo1
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104 .macro FW_CONFIG_INFO2
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105 cljmp 0x85,hrc_fw_configinfo2
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108 #ifdef _CHANGEABLE_ID_
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109 ; lesen der ID aus dem EEPROM beim Start
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111 ldi r_temp2,lo8(E2END)
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114 out _SFR_IO_ADDR(EEARH), zh
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118 rjmp read_EEPROM_ID_loop
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120 ldi r_temp2,lo8(E2END)
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123 out _SFR_IO_ADDR(EEARH), zh
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127 read_EEPROM_ID_loop:
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128 sbic _SFR_IO_ADDR(EECR), EEPE
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129 rjmp read_EEPROM_ID_loop
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130 out _SFR_IO_ADDR(EEARL),r_temp2
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131 sbi _SFR_IO_ADDR(EECR), EERE
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132 in r_rwbyte,_SFR_IO_ADDR(EEDR)
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134 breq read_EEPROM_ID_end
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139 brne read_EEPROM_ID_loop
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140 read_EEPROM_ID_end:
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151 rjmp handle_end_no_bcount // sleep eventuell reset, nichts tun und auf Timeout warten
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152 rjmp h_readromcommand
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156 rjmp h_readcommand1
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157 rjmp h_readcommand2
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158 #ifdef _HANDLE_CC_COMMAND_
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159 rjmp h_readcommand12
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161 rjmp handle_end_no_bcount
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163 rjmp h_fwconfiginfo1
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164 rjmp h_fwconfiginfo2
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165 #ifdef _CHANGEABLE_ID_
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176 cjmp 0x55,hrc_set_matchrom
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177 cjmp 0xF0,hrc_set_searchrom
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178 cjmp 0xEC,hrc_set_alarm_search
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179 #ifdef _HANDLE_CC_COMMAND_
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180 cjmp 0xCC,hrc_start_read_command12
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182 rjmp handle_end_sleep
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184 #ifndef _DIS_FLASH_
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185 ;sprung zum flasher
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187 lds r_temp,flashmarker
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189 brne hrc_jmp_flasher_inc
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194 ret ; Direkter Sprung zum Bootloader
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195 hrc_jmp_flasher_inc:
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197 sts flashmarker,r_temp
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198 rjmp handle_end_sleep
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203 sts srbyte,r_temp ; Beide geraete nehmen an searchrom teil
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204 ldi r_mode,OW_MATCHROM
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209 hrc_set_searchrom:
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211 sts srbyte,r_temp ; Beide geraete nehmen an searchrom teil
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212 configZ idtable,r_bytep
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213 rjmp h_searchrom_next_bit
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215 hrc_start_read_command: ;Skip rom und Matchrom ok...
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219 breq hrc_start_read_command1
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221 breq hrc_start_read_command2
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222 rjmp handle_end_sleep
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223 hrc_start_read_command1:
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224 ldi r_mode,OW_READ_COMMAND1
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226 hrc_start_read_command2:
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227 ldi r_mode,OW_READ_COMMAND2
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230 #ifdef _HANDLE_CC_COMMAND_
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231 hrc_start_read_command12:
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232 ldi r_mode,OW_READ_COMMAND12
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236 hrc_set_alarm_search:
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237 lds r_temp,alarmflag
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239 brne hrc_set_searchrom ;alarm flag nicht 0 also gehe zu searchrom
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241 rjmp handle_end_sleep
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243 hrc_fw_configinfo1:
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244 #ifdef _NO_CONFIGBYTES_
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245 rjmp handle_end_sleep
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247 ldi r_mode,OW_FWCONFIGINFO1
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250 rjmp h_fwconfiginfo1
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253 hrc_fw_configinfo2:
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254 #ifdef _NO_CONFIGBYTES_
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255 rjmp handle_end_sleep
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257 ldi r_mode,OW_FWCONFIGINFO2
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260 rjmp h_fwconfiginfo2
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263 ;---------------------------------------------------
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265 ;---------------------------------------------------
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269 lds r_bcount,srbyte
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270 sbrs r_bcount,0 ;ueberspringe wenn bit 1 =0 also geraet 1 nich mehr im rennen
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271 rjmp h_matchrom_id2
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272 configZ owid1,r_bytep
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274 cp r_temp2,r_rwbyte
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275 breq h_matchrom_id2
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276 cbr r_bcount,1 ; loesche geraet
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277 breq h_matchrom_sleep
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279 configZ owid2,r_bytep
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281 cp r_temp2,r_rwbyte
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283 cbr r_bcount,2 ; loesche geraet
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284 breq h_matchrom_sleep
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287 sts srbyte,r_bcount
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289 breq hrc_start_read_command ;Starten von Read Command
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290 rjmp handle_end_inc
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293 sts srbyte,r_bcount
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294 rjmp handle_end_sleep
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297 ;---------------------------------------------------
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299 ;---------------------------------------------------
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302 h_searchrom_next_bit: ;Setup next Bit of ID
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304 lds r_temp,srbyte ;srbyte ist ein zeiger auf die bits fuer ein bit im Table
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305 h_searchrom_next_bit_l2:
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307 breq h_searchrom_next_bit_l1
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311 rjmp h_searchrom_next_bit_l2
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312 h_searchrom_next_bit_l1:
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314 rol r_rwbyte ; negiertes bit in rwbyte
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316 rol r_rwbyte ; bit in rwbyte
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318 ldi r_bcount,0x40 ; zwei bits sensden dann zu Searchromr
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319 ldi r_mode,OW_SEARCHROMR
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320 rjmp handle_end_no_bcount
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324 h_searchroms: ; Modus Send zwei bit
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325 configZ idtable,r_bytep
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329 breq h_searchroms_idd
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331 breq h_searchroms_id1
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333 breq h_searchroms_id2
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334 rjmp handle_end_sleep ; zur Sicherheit.....
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337 breq h_searchroms_idd_zero
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339 sbrc r_temp2,0 ;springe wenn nicht beide bits 0 (id 1 negiert und id 2 negiert)
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340 rjmp handle_end_sleep ;
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341 sbrc r_temp2,4 ;id1 set? then skip
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342 cbr r_temp,1 ; loesche bit 1 in srbyte
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343 sbrc r_temp2,2 ; springe wenn id 2 gesetzt ist
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344 cbr r_temp,2 ; loesche bit 2 in srbyte
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346 rjmp h_searchroms_idX_end
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347 h_searchroms_idd_zero:
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348 sbrc r_temp2,1 ;springe wenn nicht beide 1 (id 1 und id 2 )
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349 rjmp handle_end_sleep ;beide 1 gehe schlafen
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350 sbrs r_temp2,4 ;id1 0? then skip
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351 cbr r_temp,1 ; loesche bit 1 in srbyte
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352 sbrs r_temp2,2 ; springe wenn id 2 null ist
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353 cbr r_temp,2 ; loesche bit 2 in srbyte
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355 rjmp h_searchroms_idX_end
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358 breq h_searchroms_id1_zero
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360 sbrs r_temp2,5 ;id1 set? then skip
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361 rjmp handle_end_sleep ;
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362 rjmp h_searchroms_idX_end
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363 h_searchroms_id1_zero:
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364 sbrs r_temp2,4 ;id1 set? then skip
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365 rjmp handle_end_sleep ;
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366 rjmp h_searchroms_idX_end
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369 breq h_searchroms_id2_zero
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371 sbrs r_temp2,3 ;id1 set? then skip
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372 rjmp handle_end_sleep ;
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373 rjmp h_searchroms_idX_end
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374 h_searchroms_id2_zero:
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375 sbrs r_temp2,2 ;id1 set? then skip
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376 rjmp handle_end_sleep ;
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377 rjmp h_searchroms_idX_end
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378 h_searchroms_idX_end:
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381 brne h_searchroms_idX_end1
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382 rjmp handle_end_sleep
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383 h_searchroms_idX_end1:
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386 breq h_searchrom_end_ok ;unterschied nur das letzt bit wird wohl nie vorkommen
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387 rjmp h_searchrom_next_bit
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389 h_searchrom_end_ok:
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391 rjmp hrc_start_read_command
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393 h_searchromr: ; stelle um auf empfangen
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395 ldi r_mode,OW_SEARCHROMS
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396 ldi r_bcount,0 ;gehe nach einem bit zu SEARCHROMS
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397 rjmp handle_end_no_bcount
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400 ;---------------------------------------------------
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402 ;---------------------------------------------------
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405 #ifdef _NO_CONFIGBYTES_
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407 rjmp handle_end_sleep
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409 configZ config_info1,r_bytep
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410 rjmp h_fwconfiginfo_go
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412 configZ config_info2,r_bytep
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415 breq h_fwconfiginfo_crc
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417 breq h_fwconfiginfo_all
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418 //h_fwconfiginfo_end:
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419 //configZ config_info1,r_bytep //crc16 wird in config_info1 gespeichert, auch bei config_info2
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420 configZ config_info2,r_bytep
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422 rjmp handle_end_inc
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428 breq h_fwconfiginfo_crc
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431 breq h_fwconfiginfo_all
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432 #elif defined _CRC16_
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434 breq h_fwconfiginfo_all
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437 breq h_fwconfiginfo_all
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438 #warning No CRC known code implemented
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441 h_fwconfiginfo_end:
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442 //configZ config_info1,r_bytep //crc16 wird in config_info1 gespeichert, auch bei config_info2
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443 //configZ config_info1,r_bytep
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445 rjmp handle_end_inc
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446 h_fwconfiginfo_crc:
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449 rjmp handle_end_inc
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450 #elif defined _CRC16_
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453 sts config_info1+24,r_temp
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456 sts config_info1+25,r_temp
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457 ldi r_mode,OW_FWCONFIGINFO1 //auch CRC vom Dev 2 wird in Configinfo 1 geschrieben also da weiter machen
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458 configZ config_info1,r_bytep
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460 rjmp handle_end_inc
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463 h_fwconfiginfo_all:
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464 rjmp handle_end_sleep
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467 ;---------------------------------------------------
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468 ; CHANGE ROM FUNCTIONS
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469 ;---------------------------------------------------
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472 #ifdef _CHANGEABLE_ID_
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475 configZ newid,r_bytep
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479 rjmp handle_end_inc
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481 rjmp handle_end_sleep
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485 ldi r_mode,OW_READ_NEWID
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490 configZ newid,r_bytep
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492 rjmp handle_end_inc
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495 rjmp handle_end_sleep
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498 ldi r_mode,OW_SET_NEWID
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499 ;ldi r_bytep,1 ;start to write in 2
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500 rjmp handle_end_inc ;set r_bytep to 1!!!
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503 lds r_bcount,srbyte
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507 configZ owid1,r_bytep
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510 configZ owid2,r_bytep
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514 brne h_setid_bad_code_all
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520 breq h_setid_copy_id
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521 rjmp h_setid_bad_code_all ;sollte eigentlich nicht passieren
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529 ldi r_temp2,lo8(E2END)
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535 ;ldi r_temp,0 ;kommt nicht vor das ein E2ROM genau n*256+(0 bis 7) byte gross ist
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537 out _SFR_IO_ADDR(EEARH),zh
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541 h_setid_EEPROM_write:
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542 sbic _SFR_IO_ADDR(EECR), EEPE
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543 rjmp h_setid_EEPROM_write
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544 ldi r_temp, (0<<EEPM1)|(0<<EEPM0)
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545 out _SFR_IO_ADDR(EECR), r_temp
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546 ;nur adresse L schreiben H bleibt aus oben genannten grund gleich.
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547 out _SFR_IO_ADDR(EEARL),r_temp2
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549 out _SFR_IO_ADDR(EEDR), r_rwbyte
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550 sbi _SFR_IO_ADDR(EECR), EEMPE
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551 sbi _SFR_IO_ADDR(EECR), EEPE
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555 brne h_setid_EEPROM_write
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556 //rcall read_EEPROM_ID1
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557 //rcall read_EEPROM_ID2
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567 h_setid_bad_code_all:
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568 rjmp handle_end_sleep
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586 ; check for bootloader jumper
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587 ;vor allen anderen Registerconfigs
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589 #ifndef _DIS_FLASH_
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590 ldi r_temp,(1<<PUD) ;enable pullup
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591 out _SFR_IO_ADDR(MCUCR) ,r_temp
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592 sbi _SFR_IO_ADDR(PORTA),PINA5 ;internal pullup on PINA5
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593 sbi _SFR_IO_ADDR(PORTA),PINA4 ;internal pullup on PINA4
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595 sbis _SFR_IO_ADDR(PINA),PINA5
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596 rjmp owinit_botest_end ;PinA5 nicht auf 1
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597 sbis _SFR_IO_ADDR(PINA),PINA4
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598 rjmp owinit_botest_end ;PinA4 nicht auf 1
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599 cbi _SFR_IO_ADDR(PORTA),PINA4
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600 sbi _SFR_IO_ADDR(DDRA),PINA4 ;PINA4 AUSGANG und 0
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602 sbic _SFR_IO_ADDR(PINA),PINA5
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603 rjmp owinit_botest_end ;PINA5 nicht 0.... nicht verbunden
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604 cbi _SFR_IO_ADDR(DDRA),PINA4
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609 ret ; Direkter Sprung zum Bootloader*/
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612 HW_INIT //Microcontroller specific
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613 CHIP_INIT //1-Wire device specific
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622 #ifdef _CHANGEABLE_ID_
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623 rcall read_EEPROM_ID1
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624 rcall read_EEPROM_ID2
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628 ldi zl,lo8(idtable)
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629 ldi zh,hi8(idtable)
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649 rol r_mode ;6. Bit id1
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651 rol r_mode ; 5. Bit id1negiert
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653 rol r_mode ;;4. Bit id2
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655 rol r_mode ;3. Bit id2 negiert
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657 rol r_mode ;zweites bit id1 und id2
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659 rol r_mode ;erstes bit id1 negiert und id2 negiert
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665 ;copy ids in config bytes
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666 #ifndef _NO_CONFIGBYTES_
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669 ldi yl,lo8(config_info2+17)
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670 ldi yh,hi8(config_info2+17)
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676 brne owinit_cpconfig1
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679 ldi yl,lo8(config_info1+17)
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680 ldi yh,hi8(config_info1+17)
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686 brne owinit_cpconfig2
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692 sts alarmflag,r_temp
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703 .global EXTERN_SLEEP
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708 sts mode,r_temp ;SLEEP
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709 sts gcontrol,r_temp
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710 sts sendflag,r_temp
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