DS18B20_ADC/DS18B20_ADC.c

   1 \r
   2 // Copyright (c) 2017, Tobias Mueller tm(at)tm3d.de\r
   3 // All rights reserved.\r
   4 //\r
   5 // Redistribution and use in source and binary forms, with or without\r
   6 // modification, are permitted provided that the following conditions are\r
   7 // met:\r
   8 //\r
   9 //  * Redistributions of source code must retain the above copyright\r
  10 //    notice, this list of conditions and the following disclaimer.\r
  11 //  * Redistributions in binary form must reproduce the above copyright\r
  12 //    notice, this list of conditions and the following disclaimer in the\r
  13 //    documentation and/or other materials provided with the\r
  14 //    distribution.\r
  15 //  * All advertising materials mentioning features or use of this\r
  16 //    software must display the following acknowledgement: This product\r
  17 //    includes software developed by tm3d.de and its contributors.\r
  18 //  * Neither the name of tm3d.de nor the names of its contributors may\r
  19 //    be used to endorse or promote products derived from this software\r
  20 //    without specific prior written permission.\r
  21 //\r
  22 // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\r
  23 // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\r
  24 // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\r
  25 // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\r
  26 // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\r
  27 // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
  28 // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\r
  29 // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\r
  30 // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\r
  31 // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
  32 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
  33 \r
  34 #define F_CPU 8000000UL\r
  35 #include <avr/io.h>\r
  36 #include <avr/interrupt.h>\r
  37 #include <util/delay.h>\r
  38 #include <avr/wdt.h>\r
  39 #include <avr/sleep.h>\r
  40 #include <avr/pgmspace.h>\r
  41 \r
  42 extern void OWINIT();\r
  43 extern void EXTERN_SLEEP();\r
  44 \r
  45 \r
  46 \r
  47 uint8_t owid[8]={0x28, 0xA2, 0xD9, 0x84, 0x00, 0x16, 0x02, 0xAC};/**/\r
  48 uint8_t config_info[26]={0x01,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x02,6,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00};\r
  49         \r
  50 #if (owid>128) \r
  51 #error "Variable not correct"\r
  52 #endif\r
  53 \r
  54 extern uint8_t mode;\r
  55 extern uint8_t gcontrol;\r
  56 extern uint8_t reset_indicator;\r
  57 extern uint8_t alarmflag;\r
  58 \r
  59 \r
  60 volatile uint8_t wdcounter;\r
  61 \r
  62 \r
  63 typedef union {\r
  64         volatile uint8_t bytes[8];\r
  65         struct {\r
  66                 uint16_t temp;  //0\r
  67                 uint8_t TH;  //2\r
  68                 uint8_t TL;  //3\r
  69                 uint8_t config;  //4\r
  70                 uint8_t rrFF; //5\r
  71                 uint8_t rr00; //6\r
  72                 uint8_t rr10; //7\r
  73         };\r
  74 } pack_t;\r
  75 volatile pack_t pack;\r
  76 \r
  77 \r
  78 \r
  79 \r
  80 #if  defined(__AVR_ATtiny24__)||defined(__AVR_ATtiny44__)  || defined(__AVR_ATtiny84__) || defined(__AVR_ATtiny24A__)||defined(__AVR_ATtiny44A__)  || defined(__AVR_ATtiny84A__)\r
  81 ISR(WATCHDOG_vect) {\r
  82 #else\r
  83 ISR(WDT_vect) {\r
  84 #endif \r
  85         //sleep_disable();          // Disable Sleep on Wakeup\r
  86         wdcounter++;\r
  87         if (reset_indicator==1) reset_indicator++;\r
  88         else if (reset_indicator==2) mode=0;\r
  89 /*      if (timeout==2) {\r
  90                 DIS_TIMER;\r
  91                 EN_OWINT;\r
  92                 mode=OWM_SLEEP;\r
  93         }\r
  94         timeout++;*/\r
  95         //sleep_enable();           // Enable Sleep Mode\r
  96 \r
  97 }\r
  98 \r
  99 \r
 100 volatile double V,ktemp;\r
 101 \r
 102 uint16_t ADmess() {\r
 103          ADMUX=0b00101100;  //3V  ADC2+  ADC1- 1x\r
 104          ADCSRA|=(1<<ADSC);\r
 105          while ((ADCSRA&(1<<ADSC)));\r
 106         return ADC;\r
 107 }\r
 108 \r
 109 int main(void){\r
 110     //PRR|=(1<<PRUSI)|(1<<PRADC);  //Switch off usi and adc for save Power\r
 111         pack.temp=0x0550;\r
 112         pack.config=0x7F;\r
 113         pack.TH=75;\r
 114         pack.TL=70;\r
 115         pack.rrFF=0xFF;\r
 116         pack.rr00=0;\r
 117         pack.rr10=0x10;\r
 118         PORTA=0xFF-(1<<PINA1)-(1<<PINA2);\r
 119         PORTB=0xFF;\r
 120         OWINIT();\r
 121 \r
 122         MCUCR &=~(1<<PUD); //All Pins Pullup...\r
 123         MCUCR |=(1<<BODS);\r
 124 \r
 125         WDTCSR |= ((1<<WDCE) );   // Enable the WD Change Bit//| (1<<WDE)\r
 126         WDTCSR |=   (1<<WDIE) |              // Enable WDT Interrupt\r
 127         (1<<WDP2) | (1<<WDP1);   // Set Timeout to ~1 seconds\r
 128         MCUSR=0;\r
 129         sei();\r
 130         ADCSRA=(1<<ADEN)|(1<<ADPS2)|(1<<ADPS1);//|(1<<ADPS0);\r
 131         \r
 132         \r
 133         uint16_t ares[16],sum;\r
 134         uint8_t par=0;\r
 135         sum=0;\r
 136         for(uint8_t i=0;i<16;i++) {\r
 137                 //sum+=ares[i];\r
 138                 sum+=ADmess();\r
 139         }\r
 140         par=0;\r
 141         wdcounter=0;\r
 142         gcontrol=1;\r
 143 \r
 144     while(1)   {\r
 145                 if (wdcounter>0) {\r
 146 //                      ares[par]=ADmess();\r
 147                         par++;\r
 148                         if (par>15) par=0;\r
 149                         wdcounter=0;\r
 150                         sum=0;\r
 151                         for(uint8_t i=0;i<16;i++) {\r
 152                                 //sum+=ares[i];\r
 153                                 sum+=ADmess();\r
 154                         }\r
 155 \r
 156 \r
 157                 }\r
 158                 if (gcontrol) {\r
 159                         PORTB|=(1<<PORTB0);\r
 160                         //V=sum/20.0/1024.0*1.12*1000.0/16.0;\r
 161                         //V=sum/20.0/1024.0*1.01*1000.0/16.0;\r
 162                         V=sum/1024.0*182-55*16-16;\r
 163                         if (V>125*16) V=125*16;\r
 164                         if (V<-55*16) V=-55*16;\r
 165                 \r
 166                         uint16_t htemp=V;\r
 167                 \r
 168                         uint8_t t8=pack.temp>>4;\r
 169                         uint8_t af=0;\r
 170                         if (t8>pack.TH) af=1;\r
 171                         if (t8<=pack.TL) af=1;\r
 172                         cli();\r
 173                         pack.temp=htemp;\r
 174                         alarmflag=af;\r
 175                         sei();\r
 176                         EXTERN_SLEEP();\r
 177                         PORTB&=~(1<<PORTB0);\r
 178                 }\r
 179 \r
 180                 \r
 181 #if  defined(__AVR_ATtiny25__)||defined(__AVR_ATtiny45__)  || defined(__AVR_ATtiny85__)\r
 182                         if (((TIMSK & (1<<TOIE0))==0)&& (mode==0))\r
 183 #endif                  \r
 184 #if  defined(__AVR_ATtiny24__)||defined(__AVR_ATtiny44__)  || defined(__AVR_ATtiny84__) ||defined(__AVR_ATtiny24A__)||defined(__AVR_ATtiny44A__)  || defined(__AVR_ATtiny84A__)\r
 185                         if (((TIMSK0 & (1<<TOIE0))==0)&& (mode==0))\r
 186 #endif\r
 187                           {\r
 188 //                      CLKPR=(1<<CLKPCE);\r
 189         //              CLKPR=(1<<CLKPS2); /*0.5Mhz*/\r
 190 //                      PORTB&=~(1<<PINB1);\r
 191                         MCUCR|=(1<<SE)|(1<<SM1);\r
 192                         MCUCR&=~(1<<ISC01);\r
 193                 } else {\r
 194                         MCUCR|=(1<<SE);\r
 195                         MCUCR&=~(1<<SM1);\r
 196                 }\r
 197                 asm("SLEEP");\r
 198    }\r
 199 \r
 200 \r
 201 }