Many changes from 2018
[owSlave2.git] / DS2450_SHT3X / DS2450_SHT3X.c
1 // Copyright (c) 2017, Tobias Mueller tm(at)tm3d.de\r
2 // All rights reserved.\r
3 //\r
4 // Redistribution and use in source and binary forms, with or without\r
5 // modification, are permitted provided that the following conditions are\r
6 // met:\r
7 //\r
8 //  * Redistributions of source code must retain the above copyright\r
9 //    notice, this list of conditions and the following disclaimer.\r
10 //  * Redistributions in binary form must reproduce the above copyright\r
11 //    notice, this list of conditions and the following disclaimer in the\r
12 //    documentation and/or other materials provided with the\r
13 //    distribution.\r
14 //  * All advertising materials mentioning features or use of this\r
15 //    software must display the following acknowledgement: This product\r
16 //    includes software developed by tm3d.de and its contributors.\r
17 //  * Neither the name of tm3d.de nor the names of its contributors may\r
18 //    be used to endorse or promote products derived from this software\r
19 //    without specific prior written permission.\r
20 //\r
21 // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\r
22 // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\r
23 // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\r
24 // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\r
25 // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\r
26 // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
27 // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\r
28 // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\r
29 // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\r
30 // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
31 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
32 \r
33 #define F_CPU 8000000UL\r
34 #include <avr/io.h>\r
35 #include <avr/interrupt.h>\r
36 #include <util/delay.h>\r
37 #include <avr/wdt.h>\r
38 #include <avr/sleep.h>\r
39 #include <avr/pgmspace.h>\r
40 #include "../common/I2C/USI_TWI_Master.h"\r
41 #include "../common/I2C/SHT3x.h"\r
42 #include "../common/calibr.h"\r
43 extern void OWINIT();\r
44 extern void EXTERN_SLEEP();\r
45 //6A02160084D9A320\r
46 //uint8_t owid[8]={0x20, 0xA2, 0xD9, 0x84, 0x00, 0x16, 0x02, 0x5D};/**/\r
47 uint8_t owid[8]={0x20, 0xA3, 0xD9, 0x84, 0x00, 0x16, 0x02, 0x6A};/**/\r
48 uint8_t config_info[26]={0x01,14,0x04,0x08, 0,0, 0,0,0x02,21,21,0x00,0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00};\r
49 #if (owid>128) \r
50 #error "Variable not correct"\r
51 #endif\r
52 \r
53 extern uint8_t mode;\r
54 extern uint8_t gcontrol;\r
55 extern uint8_t reset_indicator;\r
56 extern uint8_t alarmflag;\r
57 volatile uint8_t wdcounter=10;\r
58 \r
59 \r
60 #if  defined(__AVR_ATtiny24__)||defined(__AVR_ATtiny44__)  || defined(__AVR_ATtiny84__) || defined(__AVR_ATtiny24A__)||defined(__AVR_ATtiny44A__)  || defined(__AVR_ATtiny84A__)\r
61 ISR(WATCHDOG_vect) {\r
62 #else\r
63 ISR(WDT_vect) {\r
64 #endif \r
65         wdcounter++;\r
66         if (reset_indicator==1) reset_indicator++;\r
67         else if (reset_indicator==2) mode=0;\r
68 }\r
69 \r
70 typedef union {\r
71         volatile uint8_t bytes[0x20];\r
72         struct {\r
73                 //Page0\r
74                 uint16_t A;  //0\r
75                 uint16_t B;  //2\r
76                 uint16_t C;  //4\r
77                 uint16_t D;  //6\r
78                 //Page1\r
79                 uint8_t CSA1;\r
80                 uint8_t CSA2;\r
81                 uint8_t CSB1;\r
82                 uint8_t CSB2;\r
83                 uint8_t CSC1;\r
84                 uint8_t CSC2;\r
85                 uint8_t CSD1;\r
86                 uint8_t CSD2;\r
87                 //Page2\r
88                 uint8_t LA;\r
89                 uint8_t HA;\r
90                 uint8_t LB;\r
91                 uint8_t HB;\r
92                 uint8_t LC;\r
93                 uint8_t HC;\r
94                 uint8_t LD;\r
95                 uint8_t HD;\r
96                 //Page3\r
97                 uint8_t FC1;\r
98                 uint8_t FC2;\r
99                 uint8_t FC3;\r
100                 uint8_t FC4;\r
101                 uint8_t VCCP;\r
102                 uint8_t FC5;\r
103                 uint8_t FC6;\r
104                 uint8_t FC7;\r
105                 uint8_t convc1;\r
106                 uint8_t convc2;\r
107                 \r
108                 \r
109         };\r
110 } pack_t;\r
111 volatile pack_t pack;\r
112 \r
113 \r
114 \r
115 volatile int16_t am2302_temp;\r
116 volatile uint16_t am2302_hum;\r
117 \r
118 \r
119 uint8_t userRegister[1];\r
120 int16_t sRH,sT;\r
121  double temperatureC,humidityRH;\r
122 uint32_t P;\r
123 int32_t t;\r
124 \r
125 \r
126 \r
127 \r
128 int main(void){\r
129         pack.A=0;\r
130         pack.B=0;\r
131         pack.C=0;\r
132         pack.D=0;\r
133         pack.CSA1=0x08;\r
134         pack.CSA2=0x8C;\r
135         pack.CSB1=0x08;\r
136         pack.CSB2=0x8C;\r
137         pack.CSC1=0x08;\r
138         pack.CSC2=0x8C;\r
139         pack.CSD1=0x08;\r
140         pack.CSD2=0x8C;\r
141         pack.HA=0xFF;\r
142         pack.LA=0x00;\r
143         pack.HB=0xFF;\r
144         pack.LB=0x00;\r
145         pack.HC=0xFF;\r
146         pack.LC=0x00;\r
147         pack.HD=0xFF;\r
148         pack.LD=0x00;\r
149         pack.VCCP=0;\r
150     PORTB=0xFF-(1<<PORTB0); //Schalter kann gegen Masse sein und zieht dann immer Strom\r
151         DDRB|=(1<<PORTB0); //Als Ausgang und 0\r
152         PORTA=0xFF;  //All Pull up;\r
153          PRR|=(1<<PRADC);  // adc for save Power\r
154 \r
155         ACSR|=(1<<ACD);  //Disable Comparator\r
156         OWINIT();\r
157 \r
158         MCUCR &=~(1<<PUD); //All Pins Pullup...\r
159         MCUCR |=(1<<BODS);\r
160         WDTCSR |= ((1<<WDCE) );   // Enable the WD Change Bit//| (1<<WDE)\r
161         WDTCSR |=   (1<<WDIE) |              // Enable WDT Interrupt\r
162         (1<<WDP3) | (1<<WDP0);   // Set Timeout to ~8 seconds\r
163         \r
164         gcontrol=1;\r
165         \r
166         USI_TWI_Master_Initialise();\r
167 \r
168         initSHT3x(0);\r
169         _delay_ms(100);\r
170         getSHT3xHumTemp(0,&temperatureC,&humidityRH);\r
171 \r
172         sei();\r
173         \r
174         //DDRB|=(1<<PINB1);\r
175 \r
176     while(1)   {\r
177         \r
178         if (wdcounter>3) {      \r
179                 \r
180                 getSHT3xHumTemp(0,&temperatureC,&humidityRH);\r
181 \r
182                 wdcounter=0;\r
183         }\r
184         \r
185 \r
186                 \r
187                 \r
188 \r
189 \r
190                 if (gcontrol) {\r
191                         //PORTB|=(1<<PINB1);\r
192                         uint8_t bb=1;\r
193                         uint8_t bb1=1;\r
194                         for(uint8_t i=0;i<4;i++){\r
195                                 if (pack.convc1&bb1) {\r
196                                         if (pack.convc2&(bb)) {pack.bytes[i*2]=0;pack.bytes[i*2+1]=0;}\r
197                                         bb=bb<<1;\r
198                                         if (pack.convc2&(bb)) {pack.bytes[i*2]=0xFF;pack.bytes[i*2+1]=0xFF;}\r
199                                         bb=bb<<1;\r
200                                 } else bb=bb<<2;\r
201                                 bb1=bb1<<1;                             \r
202                         }\r
203                         //CHanel A\r
204                         if (pack.convc1&1) {\r
205                                 /*if (pack.CSA2&0x01)   ADMUX=0; else ADMUX=0x80;\r
206                                 _delay_us(100);\r
207                                 ADCSRA|=(1<<ADSC);\r
208                                 while ((ADCSRA&(1<<ADSC)));\r
209                                 cli();pack.A=ADC;sei();*/\r
210                                 uint16_t ct=(temperatureC*100.0)+32767;\r
211                                 cli();pack.A=ct;sei();\r
212                                 wdcounter=10;\r
213                                 alarmflag=0;\r
214                                 \r
215                                 if (pack.CSA2&0x08)  //AEH\r
216                                         if (pack.bytes[1]>pack.HA) {alarmflag=1;pack.CSA2|=0x20;}\r
217                                 if (pack.CSA2&0x04)  //AEL\r
218                                         if (pack.bytes[1]<pack.LA) {alarmflag=1;pack.CSA2|=0x10;}\r
219                         }\r
220 \r
221                         if (pack.convc1&2) {\r
222                                 /*if (pack.CSB2&0x01)   ADMUX=1; else ADMUX=0x81;\r
223                                 _delay_us(100);\r
224                                 ADCSRA|=(1<<ADSC);\r
225                                 while ((ADCSRA&(1<<ADSC)));\r
226                                 cli();pack.B=ADC;sei();*/\r
227                                 wdcounter=10;\r
228                                 cli();pack.B=humidityRH*100;sei();\r
229                                 if (pack.CSB2&0x08)  //AEH\r
230                                         if (pack.bytes[1]>pack.HB) {alarmflag=1;pack.CSB2|=0x20;}\r
231                                 if (pack.CSB2&0x04)  //AEL\r
232                                         if (pack.bytes[1]<pack.LB) {alarmflag=1;pack.CSB2|=0x10;}\r
233                         }\r
234 \r
235                         if (pack.convc1&4) {\r
236                                 /*if (pack.CSC2&0x01)   ADMUX=2; else ADMUX=0x82;\r
237                                 _delay_us(100);\r
238                                 ADCSRA|=(1<<ADSC);\r
239                                 while ((ADCSRA&(1<<ADSC)));\r
240                                 cli();pack.C=ADC;sei();*/\r
241                                 wdcounter=10;\r
242                                 cli();pack.C=0;sei();\r
243                                 if (pack.CSC2&0x08)  //AEH\r
244                                         if (pack.bytes[1]>pack.HC) {alarmflag=1;pack.CSC2|=0x20;}\r
245                                 if (pack.CSC2&0x04)  //AEL\r
246                                         if (pack.bytes[1]<pack.LC) {alarmflag=1;pack.CSC2|=0x10;}\r
247                         } \r
248                         if (pack.convc1&8) {\r
249                                 /*if (pack.CSD2&0x01)   ADMUX=3; else ADMUX=0x83;\r
250                                 _delay_us(100);\r
251                                 ADCSRA|=(1<<ADSC);\r
252                                 while ((ADCSRA&(1<<ADSC)));\r
253                                 cli();pack.D=ADC;sei();*/\r
254                                 wdcounter=10;\r
255                                 cli();pack.D=P/100.0*32.0;sei();\r
256                                 if (pack.CSD2&0x08)  //AEH\r
257                                         if (pack.bytes[1]>pack.HD) {alarmflag=1;pack.CSD2|=0x20;}\r
258                                 if (pack.CSD2&0x04)  //AEL\r
259                                         if (pack.bytes[1]<pack.LD) {alarmflag=1;pack.CSD2|=0x10;}\r
260                         }\r
261                         \r
262                         EXTERN_SLEEP();\r
263                         //PORTB&=~(1<<PINB1);\r
264                 }\r
265 \r
266                 /*uint8_t bb=1;\r
267                 for(uint8_t i=0;i<4;i++) {\r
268                         if (pack.bytes[8+i*2]&0x80) {  //Chanel as output\r
269                                 if (pack.bytes[8+i*2]&0x40) {\r
270                                         DDRA|=bb;\r
271                                 } else {\r
272                                         DDRA&=~bb;\r
273                                 }\r
274                         } else {\r
275                                 DDRA&=~bb;\r
276                         }\r
277                         bb=bb*2;\r
278                 }*/\r
279                 \r
280 #if  defined(__AVR_ATtiny25__)||defined(__AVR_ATtiny45__)  || defined(__AVR_ATtiny85__)\r
281                         if (((TIMSK & (1<<TOIE0))==0)&& (mode==0))\r
282 #endif                  \r
283 #if  defined(__AVR_ATtiny24__)||defined(__AVR_ATtiny44__)  || defined(__AVR_ATtiny84__) ||defined(__AVR_ATtiny24A__)||defined(__AVR_ATtiny44A__)  || defined(__AVR_ATtiny84A__)\r
284                         if (((TIMSK0 & (1<<TOIE0))==0)&& (mode==0))\r
285 #endif\r
286                           {\r
287 \r
288                         MCUCR|=(1<<SE)|(1<<SM1);\r
289                         MCUCR&=~(1<<ISC01);\r
290                 } else {\r
291                         MCUCR|=(1<<SE);\r
292                         MCUCR&=~(1<<SM1);\r
293                 }\r
294                 asm("SLEEP");\r
295    }\r
296 \r
297 \r
298 }