common/OWDS2413_DS2413.S

   1 \r
   2 // Copyright (c) 2017, Tobias Mueller tm(at)tm3d.de\r
   3 // All rights reserved. \r
   4 // \r
   5 // Redistribution and use in source and binary forms, with or without \r
   6 // modification, are permitted provided that the following conditions are \r
   7 // met: \r
   8 // \r
   9 //  * Redistributions of source code must retain the above copyright \r
  10 //    notice, this list of conditions and the following disclaimer. \r
  11 //  * Redistributions in binary form must reproduce the above copyright \r
  12 //    notice, this list of conditions and the following disclaimer in the \r
  13 //    documentation and/or other materials provided with the \r
  14 //    distribution. \r
  15 //  * All advertising materials mentioning features or use of this \r
  16 //    software must display the following acknowledgement: This product \r
  17 //    includes software developed by tm3d.de and its contributors. \r
  18 //  * Neither the name of tm3d.de nor the names of its contributors may \r
  19 //    be used to endorse or promote products derived from this software \r
  20 //    without specific prior written permission. \r
  21 // \r
  22 // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \r
  23 // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT \r
  24 // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR \r
  25 // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT \r
  26 // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, \r
  27 // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT \r
  28 // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, \r
  29 // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY \r
  30 // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT \r
  31 // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE \r
  32 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. \r
  33 \r
  34 #define _CHANGEABLE_ID_\r
  35 #define _ZERO_POLLING_\r
  36 //#define _HANDLE_CC_COMMAND_\r
  37 //#define _DB_\r
  38 //#define __4MHZ__\r
  39         \r
  40 \r
  41 #include "../common/OWConfig.s"\r
  42 #include "../common/OWCRC16.s"\r
  43 \r
  44 .extern pin_state1,1\r
  45 .extern pin_state1,1\r
  46 .extern pin_state2,1\r
  47 .extern pin_set2,1\r
  48 .comm resv1,1\r
  49 .comm resv2,1\r
  50 .macro CHIP_INIT        ;r_temp is pushed other Registers should be saved\r
  51 .endm\r
  52 \r
  53 .macro COMMAND_TABLE\r
  54 \r
  55                 rjmp h_accessread1\r
  56                 rjmp h_accesswrite1\r
  57                 rjmp h_accesswrite_read1\r
  58 \r
  59                 rjmp h_accessread2\r
  60                 rjmp h_accesswrite2\r
  61                 rjmp h_accesswrite_read2\r
  62 .endm\r
  63 \r
  64 #include "../common/OWRomFunctionsDual.s"\r
  65 #include "../common/OWTimerInterrupt.s"\r
  66 \r
  67 \r
  68 \r
  69 ; Ab hier Geraeteabhaenging\r
  70 #define OW_ACCESSREAD1 OW_FIRST_COMMAND+0\r
  71 #define OW_ACCESSWRITE1 OW_FIRST_COMMAND+1\r
  72 #define OW_ACCESSWRITE_READ1 OW_FIRST_COMMAND+2\r
  73 \r
  74 \r
  75 #define OW_ACCESSREAD2 OW_FIRST_COMMAND+3\r
  76 #define OW_ACCESSWRITE2 OW_FIRST_COMMAND+4\r
  77 #define OW_ACCESSWRITE_READ2 OW_FIRST_COMMAND+5\r
  78 \r
  79 \r
  80 ;---------------------------------------------------\r
  81 ;       READ COMMAND and start operation\r
  82 ;---------------------------------------------------\r
  83 \r
  84 h_readcommand1:\r
  85         clr r_bytep\r
  86 #ifndef _DIS_FLASH_\r
  87         FLASH_COMMANDS ; muss zu erst sein....\r
  88 #endif\r
  89         cjmp 0xF5,hrc_accessread1\r
  90         cset 0x5A,OW_ACCESSWRITE1\r
  91 /*      cset 0xBE,OW_READ_SCRATCHPAD_ADR2\r
  92         cset 0x4E,OW_WRITE_SCRATCHPAD_ADR2\r
  93         cjmp 0x44,hrc_set_convertT2\r
  94         cjmp 0xB4,hrc_set_convertV2*/\r
  95         FW_CONFIG_INFO1\r
  96         //cljmp 0x85,hrc_fw_configinfo2\r
  97 #ifdef _CHANGEABLE_ID_\r
  98         CHANGE_ID_COMMANDS\r
  99 #endif\r
 100         rjmp handle_end_sleep\r
 101 \r
 102 \r
 103 hrc_accessread1:\r
 104         ldi r_sendflag,1\r
 105         ldi r_mode,OW_ACCESSREAD1\r
 106 h_accessread1:\r
 107         lds r_temp,pin_state1\r
 108         andi r_temp,0x0F\r
 109         mov r_rwbyte,r_temp\r
 110         com r_rwbyte\r
 111         swap r_rwbyte\r
 112         andi r_rwbyte,0xF0\r
 113         or r_rwbyte,r_temp\r
 114         rjmp handle_end\r
 115 \r
 116 \r
 117 \r
 118 \r
 119 h_accesswrite_read1:\r
 120         //lds r_rwbyte,pin_state1\r
 121         rjmp handle_end_sleep\r
 122         \r
 123 \r
 124 \r
 125 h_accesswrite1:\r
 126         cpi  r_bytep,1\r
 127         breq h_accesswrite_compl1\r
 128         sts resv1,r_rwbyte\r
 129         rjmp handle_end_inc\r
 130 h_accesswrite_compl1:\r
 131         com r_rwbyte\r
 132         lds r_temp,resv1\r
 133         cp r_temp,r_rwbyte\r
 134         brne h_accesswrite_error1\r
 135         sts  pin_set1,r_rwbyte\r
 136         ldi r_mode,OW_ACCESSWRITE_READ1\r
 137         ldi r_rwbyte,0xAA\r
 138         ldi r_sendflag,1\r
 139         rjmp handle_end_inc\r
 140 h_accesswrite_error1:\r
 141         rjmp handle_end_sleep\r
 142 \r
 143 \r
 144 \r
 145 \r
 146 \r
 147 \r
 148 ;*****************************************************************************************************************************************************************************************\r
 149 ;*****************************************************************************************************************************************************************************************\r
 150 ;*****************************************************************************************************************************************************************************************\r
 151 ;*****************************************************************************************************************************************************************************************\r
 152 ;*****************************************************************************************************************************************************************************************\r
 153 \r
 154 \r
 155 h_readcommand2:\r
 156         clr r_bytep\r
 157 #ifndef _DIS_FLASH_\r
 158         FLASH_COMMANDS ; muss zu erst sein....\r
 159 #endif\r
 160         cjmp 0xF5,hrc_accessread2\r
 161         cset 0x5A,OW_ACCESSWRITE2\r
 162 /*      cset 0xBE,OW_READ_SCRATCHPAD_ADR2\r
 163         cset 0x4E,OW_WRITE_SCRATCHPAD_ADR2\r
 164         cjmp 0x44,hrc_set_convertT2\r
 165         cjmp 0xB4,hrc_set_convertV2*/\r
 166         FW_CONFIG_INFO2\r
 167         //cljmp 0x85,hrc_fw_configinfo2\r
 168 #ifdef _CHANGEABLE_ID_\r
 169         CHANGE_ID_COMMANDS\r
 170 #endif\r
 171         rjmp handle_end_sleep\r
 172 \r
 173 \r
 174 hrc_accessread2:\r
 175         ldi r_sendflag,1\r
 176         ldi r_mode,OW_ACCESSREAD2\r
 177 h_accessread2:\r
 178         lds r_temp,pin_state2\r
 179         andi r_temp,0x0F\r
 180         mov r_rwbyte,r_temp\r
 181         com r_rwbyte\r
 182         swap r_rwbyte\r
 183         andi r_rwbyte,0xF0\r
 184         or r_rwbyte,r_temp\r
 185         rjmp handle_end\r
 186 \r
 187 \r
 188 \r
 189 \r
 190 h_accesswrite_read2:\r
 191         //lds r_rwbyte,pin_state2\r
 192         rjmp handle_end_sleep\r
 193         \r
 194 \r
 195 \r
 196 h_accesswrite2:\r
 197         cpi  r_bytep,1\r
 198         breq h_accesswrite_compl2\r
 199         sts resv2,r_rwbyte\r
 200         rjmp handle_end_inc\r
 201 h_accesswrite_compl2:\r
 202         com r_rwbyte\r
 203         lds r_temp,resv2\r
 204         cp r_temp,r_rwbyte\r
 205         brne h_accesswrite_error2\r
 206         sts  pin_set2,r_rwbyte\r
 207         ldi r_mode,OW_ACCESSWRITE_READ2\r
 208         ldi r_rwbyte,0xAA\r
 209         ldi r_sendflag,1\r
 210         rjmp handle_end_inc\r
 211 h_accesswrite_error2:\r
 212         rjmp handle_end_sleep\r
 213 /*\r
 214 ;---------------------------------------------------\r
 215 ;   WRITE SCRATCHPAD\r
 216 ;---------------------------------------------------\r
 217 h_writescratchpad_adr2:\r
 218         lsl r_rwbyte\r
 219         lsl r_rwbyte\r
 220         lsl r_rwbyte\r
 221 #if  defined(__AVR_ATtiny25__)\r
 222         andi r_rwbyte,0x01 ;nur Page 0 und 1 und das immer wiederholen\r
 223 #endif\r
 224         sts block,r_rwbyte\r
 225         ldi r_mode,OW_WRITE_SCRATCHPAD2\r
 226         ldi  r_bcount,1 \r
 227         rjmp handle_end \r
 228 h_writescratchpad2:\r
 229         cpi  r_bytep,8\r
 230         breq h_writescratchpad_all2\r
 231         lds  r_temp,block\r
 232         add  r_temp,r_bytep\r
 233         configZ pack2,r_temp\r
 234         st   Z,r_rwbyte\r
 235         rjmp handle_end_inc\r
 236 h_writescratchpad_all2:\r
 237         rjmp handle_end_sleep\r
 238 \r
 239 \r
 240 \r
 241 \r
 242 \r
 243 \r
 244         */\r
 245 \r
 246 \r
 247 #include "../common/OWPinInterrupt.s"\r
 248 .end\r