--- /dev/null
+\r
+// Copyright (c) 2018, Tobias Mueller tm(at)tm3d.de\r
+// All rights reserved. \r
+// \r
+// Redistribution and use in source and binary forms, with or without \r
+// modification, are permitted provided that the following conditions are \r
+// met: \r
+// \r
+// * Redistributions of source code must retain the above copyright \r
+// notice, this list of conditions and the following disclaimer. \r
+// * Redistributions in binary form must reproduce the above copyright \r
+// notice, this list of conditions and the following disclaimer in the \r
+// documentation and/or other materials provided with the \r
+// distribution. \r
+// * All advertising materials mentioning features or use of this \r
+// software must display the following acknowledgement: This product \r
+// includes software developed by tm3d.de and its contributors. \r
+// * Neither the name of tm3d.de nor the names of its contributors may \r
+// be used to endorse or promote products derived from this software \r
+// without specific prior written permission. \r
+// \r
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \r
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT \r
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR \r
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT \r
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, \r
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT \r
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, \r
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY \r
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT \r
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE \r
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. \r
+\r
+#define _CHANGEABLE_ID_\r
+#define _ZERO_POLLING_\r
+\r
+#include "../common/OWConfig.s"\r
+#include "../common/OWCRC16.s"\r
+\r
+.extern pack1,20\r
+.extern pack2,20\r
+\r
+//Bleiben gleich denn es werden nicht beide gleichzeitig abgefragt\r
+.comm addr,1 ;zweites Adressbyte ist unnoetig (Warum auch immer fuer 32 Byte 16 Bit Adressen verwendet werden....)\r
+.comm crcsave,1 ; zwischenspeicherspeicher fuer crc nur zweites byte....\r
+//.extern am2302_temp,2\r
+\r
+.comm gcontrol1,1\r
+.comm gcontrol2,1\r
+\r
+.macro CHIP_INIT \r
+.endm\r
+\r
+.macro COMMAND_TABLE\r
+ rjmp h_readmemoryaddr1\r
+ rjmp h_readmemory1\r
+ rjmp h_readmemorycrc11\r
+ rjmp h_readmemorycrc21\r
+ rjmp h_writememoryaddr1\r
+ rjmp h_writememory1\r
+ rjmp h_writememorycrc11\r
+ rjmp h_writememorycrc21\r
+ rjmp h_writememoryreadback1\r
+ rjmp h_convert1\r
+ rjmp h_convertcrc11\r
+ rjmp h_convertcrc21\r
+ rjmp h_convert_conv1\r
+\r
+ rjmp h_readmemoryaddr2\r
+ rjmp h_readmemory2\r
+ rjmp h_readmemorycrc12\r
+ rjmp h_readmemorycrc22\r
+ rjmp h_writememoryaddr2\r
+ rjmp h_writememory2\r
+ rjmp h_writememorycrc12\r
+ rjmp h_writememorycrc22\r
+ rjmp h_writememoryreadback2\r
+ rjmp h_convert2\r
+ rjmp h_convertcrc12\r
+ rjmp h_convertcrc22\r
+ rjmp h_convert_conv2\r
+.endm\r
+\r
+#include "../common/OWRomFunctionsDual.s"\r
+#include "../common/OWTimerInterrupt.s"\r
+\r
+\r
+\r
+; Ab hier Geraeteabhaenging\r
+#define OW_READ_MEMORY_ADDR1 OW_FIRST_COMMAND+0\r
+#define OW_READ_MEMORY1 OW_FIRST_COMMAND+1\r
+#define OW_READ_MEMORY_CRC11 OW_FIRST_COMMAND+2\r
+#define OW_READ_MEMORY_CRC21 OW_FIRST_COMMAND+3\r
+#define OW_WRITE_MEMORY_ADDR1 OW_FIRST_COMMAND+4\r
+#define OW_WRITE_MEMORY1 OW_FIRST_COMMAND+5\r
+#define OW_WRITE_MEMORY_CRC11 OW_FIRST_COMMAND+6\r
+#define OW_WRITE_MEMORY_CRC21 OW_FIRST_COMMAND+7\r
+#define OW_WRITE_MEMORY_READBACK1 OW_FIRST_COMMAND+8\r
+#define OW_CONVERT1 OW_FIRST_COMMAND+9\r
+#define OW_CONVERT_CRC11 OW_FIRST_COMMAND+10\r
+#define OW_CONVERT_CRC21 OW_FIRST_COMMAND+11\r
+#define OW_CONVERT_CONV1 OW_FIRST_COMMAND+12\r
+\r
+#define OW_READ_MEMORY_ADDR2 OW_FIRST_COMMAND+13\r
+#define OW_READ_MEMORY2 OW_FIRST_COMMAND+14\r
+#define OW_READ_MEMORY_CRC12 OW_FIRST_COMMAND+15\r
+#define OW_READ_MEMORY_CRC22 OW_FIRST_COMMAND+16\r
+#define OW_WRITE_MEMORY_ADDR2 OW_FIRST_COMMAND+17\r
+#define OW_WRITE_MEMORY2 OW_FIRST_COMMAND+18\r
+#define OW_WRITE_MEMORY_CRC12 OW_FIRST_COMMAND+19\r
+#define OW_WRITE_MEMORY_CRC22 OW_FIRST_COMMAND+20\r
+#define OW_WRITE_MEMORY_READBACK2 OW_FIRST_COMMAND+21\r
+#define OW_CONVERT2 OW_FIRST_COMMAND+22\r
+#define OW_CONVERT_CRC12 OW_FIRST_COMMAND+23\r
+#define OW_CONVERT_CRC22 OW_FIRST_COMMAND+24\r
+#define OW_CONVERT_CONV2 OW_FIRST_COMMAND+25\r
+\r
+\r
+\r
+;---------------------------------------------------\r
+; READ COMMAND and start operation\r
+;---------------------------------------------------\r
+\r
+\r
+h_readcommand1:\r
+ clr r_bytep\r
+#ifndef _DIS_FLASH_\r
+ FLASH_COMMANDS ; muss zu erst sein....\r
+#endif\r
+ cset 0xAA,OW_READ_MEMORY_ADDR1\r
+ cset 0x55,OW_WRITE_MEMORY_ADDR1\r
+ cset 0x3C,OW_CONVERT1\r
+ FW_CONFIG_INFO1\r
+#ifdef _CHANGEABLE_ID_\r
+ CHANGE_ID_COMMANDS\r
+#endif\r
+ ldi r_mode,OW_SLEEP\r
+ rjmp handle_end\r
+\r
+\r
+h_readmemoryaddr1:\r
+ cpi r_bytep,0 ;erstes Adressbyte ?\r
+ brne h_readmemory_addr_byte11 ;nein dann weiter\r
+ andi r_rwbyte,0x1F ; nur Adressen zwischen 0 und 0x1F zulassen\r
+ sts addr,r_rwbyte ;speichern des ersten bytes\r
+ rjmp handle_end_inc\r
+h_readmemory_addr_byte11: ;zweiters Addressbyte wird nicht gespeichert!\r
+ ldi r_mode,OW_READ_MEMORY1 ;weiter zu read Memory\r
+ ;;ldi r_bcount,1 ;ist unten\r
+ ldi r_sendflag,1 ;jetzt sendet der Slave zum Master\r
+ clr r_bytep\r
+ rjmp h_readmemory21\r
+h_readmemory1:\r
+ lds r_bytep,addr\r
+ inc r_bytep\r
+ sts addr,r_bytep\r
+ andi r_bytep,0x07\r
+ breq h_readmemory_init_crc1\r
+h_readmemory21:\r
+ lds r_bytep,addr\r
+ ;andi r_bytep,0x1F ist oben\r
+ configZ pack1,r_bytep\r
+ ld r_rwbyte,Z\r
+ ;ldi r_bcount,1\r
+ rjmp handle_end ;sendet das Byte und geht zu h_readmemory\r
+h_readmemory_init_crc1:; init erstes CRC byte\r
+ lds r_rwbyte,crc\r
+ com r_rwbyte\r
+ lds r_temp,crc+1\r
+ com r_temp\r
+ sts crcsave,r_temp\r
+ ldi r_mode,OW_READ_MEMORY_CRC11\r
+ ;ldi r_bcount,1\r
+ rjmp handle_end\r
+h_readmemory_end1:\r
+ ldi r_mode,OW_SLEEP\r
+ clr r_sendflag\r
+ rjmp handle_end\r
+h_readmemorycrc11:;init zweites CRC Byte\r
+ lds r_rwbyte,crcsave\r
+ ;ldi r_bcount,1\r
+ ldi r_mode,OW_READ_MEMORY_CRC21\r
+ rjmp handle_end\r
+h_readmemorycrc21:;weiteres senden..... nach zweitem Byte\r
+ lds r_temp,addr\r
+ andi r_temp,0xE0\r
+ brne h_readmemory_end1; ende des speichers\r
+ ldi r_mode,OW_READ_MEMORY1\r
+ CRCInit1 ;Start with new CRC\r
+ rjmp h_readmemory21\r
+\r
+h_writememoryaddr1:\r
+ cpi r_bytep,0 ;erstes Adressbyte ?\r
+ brne h_writememory_addr_byte11 ;nein dann weiter\r
+ andi r_rwbyte,0x1F ; nur Adressen zwischen 0 und 0x1F zulassen\r
+ sts addr,r_rwbyte ;speichern des ersten bytes\r
+ inc r_bytep\r
+ ;ldi r_bcount,1\r
+ rjmp handle_end\r
+h_writememory_addr_byte11: ;zweiters Addressbyte wird nicht gespeichert!\r
+ ldi r_mode,OW_WRITE_MEMORY1 ;weiter zu read Memory\r
+ ;ldi r_bcount,1 ;; _________________________________________________in handle_end integrieren.....\r
+ lds r_bytep,addr\r
+ rjmp handle_end ;read Memory Byte\r
+h_writememory1:\r
+ lds r_bytep,addr\r
+ configZ pack1,r_bytep\r
+ st Z,r_rwbyte\r
+ ;ldi r_bcount,1\r
+ ldi r_mode,OW_WRITE_MEMORY_CRC11\r
+ ldi r_sendflag,1 ;jetzt sendet der Slave zum Master\r
+ lds r_rwbyte,crc\r
+ com r_rwbyte\r
+ lds r_temp,crc+1\r
+ com r_temp\r
+ sts crcsave,r_temp\r
+ rjmp handle_end\r
+h_writememorycrc11:\r
+ lds r_rwbyte,crcsave\r
+ ;ldi r_bcount,1\r
+ ldi r_mode,OW_WRITE_MEMORY_CRC21\r
+ rjmp handle_end\r
+h_writememorycrc21:\r
+ lds r_temp,addr\r
+ configZ pack1,r_temp\r
+ ld r_rwbyte,Z\r
+ ;ldi r_bcount,1\r
+ ldi r_mode,OW_WRITE_MEMORY_READBACK1\r
+ rjmp handle_end\r
+h_writememoryreadback1:\r
+ ldi r_temp,0x00\r
+ sts crc+1,r_temp\r
+ lds r_temp,addr\r
+ inc r_temp\r
+ sts addr,r_temp\r
+ sts crc,r_temp\r
+ ldi r_sendflag,0\r
+ ;ldi r_bcount,1\r
+ ldi r_mode,OW_WRITE_MEMORY1\r
+ rjmp handle_end\r
+\r
+h_convert1:\r
+ cpi r_bytep,0 ;erstes Adressbyte ?\r
+ brne h_convert_byte11 ;nein dann weiter\r
+ inc r_bytep\r
+ sts pack1+0x20,r_rwbyte\r
+ ;ldi r_bcount,1\r
+ rjmp handle_end\r
+h_convert_byte11: ;zweies byte glesen go crc#\r
+ sts pack1+0x21,r_rwbyte\r
+ lds r_rwbyte,crc\r
+ com r_rwbyte\r
+ lds r_temp,crc+1\r
+ com r_temp\r
+ sts crcsave,r_temp\r
+ ldi r_mode,OW_CONVERT_CRC11\r
+ ;ldi r_bcount,1\r
+ ldi r_sendflag,1\r
+ rjmp handle_end \r
+h_convertcrc11:\r
+ lds r_rwbyte,crcsave\r
+ ;ldi r_bcount,1\r
+ ldi r_mode,OW_CONVERT_CRC21\r
+ rjmp handle_end\r
+h_convertcrc21:\r
+ ldi r_temp,1\r
+ sts gcontrol1,r_temp\r
+ ;ldi r_bcount,1\r
+ ldi r_mode,OW_CONVERT_CONV1\r
+ ;clr r_sendflag\r
+ ldi r_sendflag,3 ;set bit 0 and 1 for no zero polling\r
+h_convert_conv1:\r
+ ldi r_bcount,0\r
+ ldi r_rwbyte,0\r
+ rjmp handle_end_no_bcount\r
+\r
+/////////////////////////////////////////////////////////////////////\r
+\r
+\r
+;---------------------------------------------------\r
+; READ COMMAND and start operation\r
+;---------------------------------------------------\r
+\r
+\r
+h_readcommand2:\r
+ clr r_bytep\r
+#ifndef _DIS_FLASH_\r
+ FLASH_COMMANDS ; muss zu erst sein....\r
+#endif\r
+ cset 0xAA,OW_READ_MEMORY_ADDR2\r
+ cset 0x55,OW_WRITE_MEMORY_ADDR2\r
+ cset 0x3C,OW_CONVERT2\r
+ FW_CONFIG_INFO2\r
+#ifdef _CHANGEABLE_ID_\r
+ CHANGE_ID_COMMANDS\r
+#endif\r
+ ldi r_mode,OW_SLEEP\r
+ rjmp handle_end\r
+\r
+\r
+h_readmemoryaddr2:\r
+ cpi r_bytep,0 ;erstes Adressbyte ?\r
+ brne h_readmemory_addr_byte12 ;nein dann weiter\r
+ andi r_rwbyte,0x1F ; nur Adressen zwischen 0 und 0x1F zulassen\r
+ sts addr,r_rwbyte ;speichern des ersten bytes\r
+ rjmp handle_end_inc\r
+h_readmemory_addr_byte12: ;zweiters Addressbyte wird nicht gespeichert!\r
+ ldi r_mode,OW_READ_MEMORY2 ;weiter zu read Memory\r
+ ;;ldi r_bcount,1 ;ist unten\r
+ ldi r_sendflag,1 ;jetzt sendet der Slave zum Master\r
+ clr r_bytep\r
+ rjmp h_readmemory22\r
+h_readmemory2:\r
+ lds r_bytep,addr\r
+ inc r_bytep\r
+ sts addr,r_bytep\r
+ andi r_bytep,0x07\r
+ breq h_readmemory_init_crc2\r
+h_readmemory22:\r
+ lds r_bytep,addr\r
+ ;andi r_bytep,0x1F ist oben\r
+ configZ pack2,r_bytep\r
+ ld r_rwbyte,Z\r
+ ;ldi r_bcount,1\r
+ rjmp handle_end ;sendet das Byte und geht zu h_readmemory\r
+h_readmemory_init_crc2:; init erstes CRC byte\r
+ lds r_rwbyte,crc\r
+ com r_rwbyte\r
+ lds r_temp,crc+1\r
+ com r_temp\r
+ sts crcsave,r_temp\r
+ ldi r_mode,OW_READ_MEMORY_CRC12\r
+ ;ldi r_bcount,1\r
+ rjmp handle_end\r
+h_readmemory_end2:\r
+ ldi r_mode,OW_SLEEP\r
+ clr r_sendflag\r
+ rjmp handle_end\r
+h_readmemorycrc12:;init zweites CRC Byte\r
+ lds r_rwbyte,crcsave\r
+ ;ldi r_bcount,1\r
+ ldi r_mode,OW_READ_MEMORY_CRC22\r
+ rjmp handle_end\r
+h_readmemorycrc22:;weiteres senden..... nach zweitem Byte\r
+ lds r_temp,addr\r
+ andi r_temp,0xE0\r
+ brne h_readmemory_end2; ende des speichers\r
+ ldi r_mode,OW_READ_MEMORY2\r
+ CRCInit1 ;Start with new CRC\r
+ rjmp h_readmemory22\r
+\r
+h_writememoryaddr2:\r
+ cpi r_bytep,0 ;erstes Adressbyte ?\r
+ brne h_writememory_addr_byte12 ;nein dann weiter\r
+ andi r_rwbyte,0x1F ; nur Adressen zwischen 0 und 0x1F zulassen\r
+ sts addr,r_rwbyte ;speichern des ersten bytes\r
+ inc r_bytep\r
+ ;ldi r_bcount,1\r
+ rjmp handle_end\r
+h_writememory_addr_byte12: ;zweiters Addressbyte wird nicht gespeichert!\r
+ ldi r_mode,OW_WRITE_MEMORY2 ;weiter zu read Memory\r
+ ;ldi r_bcount,1 ;; _________________________________________________in handle_end integrieren.....\r
+ lds r_bytep,addr\r
+ rjmp handle_end ;read Memory Byte\r
+h_writememory2:\r
+ lds r_bytep,addr\r
+ configZ pack2,r_bytep\r
+ st Z,r_rwbyte\r
+ ;ldi r_bcount,1\r
+ ldi r_mode,OW_WRITE_MEMORY_CRC12\r
+ ldi r_sendflag,1 ;jetzt sendet der Slave zum Master\r
+ lds r_rwbyte,crc\r
+ com r_rwbyte\r
+ lds r_temp,crc+1\r
+ com r_temp\r
+ sts crcsave,r_temp\r
+ rjmp handle_end\r
+h_writememorycrc12:\r
+ lds r_rwbyte,crcsave\r
+ ;ldi r_bcount,1\r
+ ldi r_mode,OW_WRITE_MEMORY_CRC22\r
+ rjmp handle_end\r
+h_writememorycrc22:\r
+ lds r_temp,addr\r
+ configZ pack2,r_temp\r
+ ld r_rwbyte,Z\r
+ ;ldi r_bcount,1\r
+ ldi r_mode,OW_WRITE_MEMORY_READBACK2\r
+ rjmp handle_end\r
+h_writememoryreadback2:\r
+ ldi r_temp,0x00\r
+ sts crc+1,r_temp\r
+ lds r_temp,addr\r
+ inc r_temp\r
+ sts addr,r_temp\r
+ sts crc,r_temp\r
+ ldi r_sendflag,0\r
+ ;ldi r_bcount,1\r
+ ldi r_mode,OW_WRITE_MEMORY2\r
+ rjmp handle_end\r
+\r
+h_convert2:\r
+ cpi r_bytep,0 ;erstes Adressbyte ?\r
+ brne h_convert_byte12 ;nein dann weiter\r
+ inc r_bytep\r
+ sts pack2+0x20,r_rwbyte\r
+ ;ldi r_bcount,1\r
+ rjmp handle_end\r
+h_convert_byte12: ;zweies byte glesen go crc#\r
+ sts pack2+0x21,r_rwbyte\r
+ lds r_rwbyte,crc\r
+ com r_rwbyte\r
+ lds r_temp,crc+1\r
+ com r_temp\r
+ sts crcsave,r_temp\r
+ ldi r_mode,OW_CONVERT_CRC12\r
+ ;ldi r_bcount,1\r
+ ldi r_sendflag,1\r
+ rjmp handle_end \r
+h_convertcrc12:\r
+ lds r_rwbyte,crcsave\r
+ ;ldi r_bcount,1\r
+ ldi r_mode,OW_CONVERT_CRC22\r
+ rjmp handle_end\r
+h_convertcrc22:\r
+ ldi r_temp,1\r
+ sts gcontrol2,r_temp\r
+ ;ldi r_bcount,1\r
+ ldi r_mode,OW_CONVERT_CONV2\r
+ ;clr r_sendflag\r
+ ldi r_sendflag,3 ;set bit 0 and 1 for no zero polling\r
+h_convert_conv2:\r
+ ldi r_bcount,0\r
+ ldi r_rwbyte,0\r
+ rjmp handle_end_no_bcount\r
+\r
+\r
+\r
+#include "../common/OWPinInterrupt.s"\r
+.end
\ No newline at end of file
tm3d / owSlave2.git / blobdiff