--- /dev/null
+// Copyright (c) 2017, Tobias Mueller tm(at)tm3d.de\r
+// All rights reserved. \r
+// \r
+// Redistribution and use in source and binary forms, with or without \r
+// modification, are permitted provided that the following conditions are \r
+// met: \r
+// \r
+// * Redistributions of source code must retain the above copyright \r
+// notice, this list of conditions and the following disclaimer. \r
+// * Redistributions in binary form must reproduce the above copyright \r
+// notice, this list of conditions and the following disclaimer in the \r
+// documentation and/or other materials provided with the \r
+// distribution. \r
+// * All advertising materials mentioning features or use of this \r
+// software must display the following acknowledgement: This product \r
+// includes software developed by tm3d.de and its contributors. \r
+// * Neither the name of tm3d.de nor the names of its contributors may \r
+// be used to endorse or promote products derived from this software \r
+// without specific prior written permission. \r
+// \r
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \r
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT \r
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR \r
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT \r
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, \r
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT \r
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, \r
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY \r
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT \r
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE \r
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. \r
+\r
+\r
+#define OW_PORT _SFR_IO_ADDR(PORTD) //1 Wire Port\r
+#define OW_PIN _SFR_IO_ADDR(PIND) //1 Wire Pin as number\r
+#define OW_PINN PORTD2\r
+#define OW_DDR _SFR_IO_ADDR(DDRD) //pin direction register\r
+\r
+#define TCNT_REG _SFR_IO_ADDR(TCNT0)\r
+\r
+\r
+#define DB_PORT _SFR_IO_ADDR(PORTB) //DEBUG\r
+#define DB_PIN _SFR_IO_ADDR(PINB) //DEBUG\r
+#define DB_DDR _SFR_IO_ADDR(DDRB) //DEBUG\r
+#define DB_PINN PORTB1\r
+\r
+#define SETZEROMARKER sbi _SFR_IO_ADDR(DDRC),6\r
+#define RESETZEROMARKER cbi _SFR_IO_ADDR(DDRC),6\r
+#define TESTZEROMARKER sbic _SFR_IO_ADDR(DDRC),6\r
+\r
+#ifdef _DB_\r
+#define sdb sbi _SFR_IO_ADDR(PORTB),DB_PINN\r
+#define cdb cbi _SFR_IO_ADDR(PORTB),DB_PINN\r
+#else\r
+#define sdb\r
+#define cdb\r
+#endif\r
+\r
+#define TIMER_INTERRUPT TIMER0_OVF_vect\r
+#define PIN_INTERRUPT INT0_vect\r
+\r
+\r
+//#define OWT_MIN_RESET 160 \r
+//#define OWT_RESET2 40\r
+//#define OWT_RESET_PRESENT 15\r
+//#define OWT_PRESENT 50\r
+//#define OWT_WRITE 18\r
+//#define OWT_READ 4\r
+#ifdef __4MHZ__\r
+#define OWT_MIN_RESET 80\r
+#define OWT_RESET2 30\r
+#define OWT_RESET_PRESENT 15\r
+#define OWT_PRESENT 60\r
+#define OWT_WRITE 16\r
+#define OWT_READ 5\r
+#define OWT_ZP_WAIT_LOW_TO 36 ; Zeit fuer die Maximale Lowzeit bei der Zerro Polling pruefung. Ist die Leitung laenger low, ist es vieleicht ein Reset \r
+#define OWT_ZP_WAIT_HIGH_TO 54 ; Zeit fuer die Maximale Hight zeit bis zu einem Low Impuls vom Master. Nach laengeren Pausen wird nicht mehr gepollt sondern der Interrup vererndet.\r
+#else\r
+#define OWT_MIN_RESET 180\r
+#define OWT_RESET2 80\r
+#define OWT_RESET_PRESENT 30\r
+#define OWT_PRESENT 130\r
+#define OWT_WRITE 35\r
+#define OWT_READ 12\r
+#define OWT_ZP_WAIT_LOW_TO 60 ; Zeit fuer die Maximale Lowzeit bei der Zerro Polling pruefung. Ist die Leitung laenger low, ist es vieleicht ein Reset \r
+#define OWT_ZP_WAIT_HIGH_TO 90 ; Zeit fuer die Maximale Hight zeit bis zu einem Low Impuls vom Master. Nach laengeren Pausen wird nicht mehr gepollt sondern der Interrup vererndet.\r
+#endif\r
+\r
+.macro CLEAR_TOV_FLAG\r
+ ldi r_temp,1\r
+ out _SFR_IO_ADDR(TIFR0),r_temp\r
+.endm\r
+\r
+.macro JMP_NO_TOV\r
+ in r_temp, _SFR_IO_ADDR(TIFR0)\r
+ sbrc r_temp,TOV0 ; wenn ueberlauf gleich weiter\r
+.endm\r
+\r
+.macro CLEAR_INTERRUPT_FLAG \r
+ ldi r_temp,(1<<INTF0);inerrupt flags durch 1 loeschen..... 0 macht nix\r
+ out _SFR_IO_ADDR(EIFR),r_temp\r
+.endm\r
+\r
+.macro EN_TIM_INT\r
+ ldi r_temp,(1<<TOIE0)\r
+ sts TIMSK0,r_temp\r
+ ldi r_temp,(1<<TOV0) ;inerrupt flags durch 1 loeschen..... 0 macht nix\r
+ out _SFR_IO_ADDR(TIFR0),r_temp\r
+.endm\r
+\r
+.macro DIS_TIM_INT\r
+ ldi r_temp,0\r
+ sts TIMSK0,r_temp\r
+.endm\r
+\r
+//Wiederherstellen von Idle mode und umschalten von Low-Level interrupt zu Falling edge\r
+.macro SET_FALLING_RESET_SLEEP\r
+ lds r_temp,EICRA\r
+ ori r_temp,(1<<ISC01)\r
+ sts EICRA,r_temp\r
+ lds r_temp,SMCR\r
+ andi r_temp,~(1<<SM1)\r
+ sts SMCR,r_temp\r
+.endm\r
+\r
+.macro HW_INIT ;r_temp is pushed other Registers should be saved\r
+ ;set clock to 8 MHz\r
+ ldi r_temp,0x80;\r
+ sts CLKPR,r_temp\r
+ //ldi r_temp,(1<<CLKPS0)\r
+#ifdef __4MHZ__\r
+ ldi r_temp,0x01;\r
+#else\r
+ ldi r_temp,0\r
+#endif\r
+ sts CLKPR,r_temp\r
+ ;Disable Timer int\r
+ ldi r_temp,0\r
+ sts TIMSK0,r_temp ;; is default\r
+ ;Enable Pin int\r
+ ldi r_temp,(1<<INT0)\r
+ out _SFR_IO_ADDR(EIMSK),r_temp\r
+ ;Set Timerclock to Clock / 8 (2us bei 4MHz) bzw 1us bei 8 MHz\r
+ ldi r_temp,(1<<CS01)\r
+ out _SFR_IO_ADDR(TCCR0B),r_temp\r
+ ;OWPin as input\r
+ cbi OW_DDR,OW_PINN ;; is default.... \r
+ cbi OW_PORT,OW_PINN ;; vereinfachung im Hauptprogram (PORTB=0xFF) wegen pullup\r
+ ;set falling edge\r
+ ldi r_temp,(1<<ISC01)\r
+ sts EICRA,r_temp\r
+#ifdef _DB_\r
+ sbi DB_DDR,DB_PINN\r
+#endif\r
+.endm\r
+\r
+.macro JMP_FLASHER\r
+ ldi r_temp,0x00\r
+ push r_temp\r
+ ldi r_temp,0x3E\r
+ push r_temp\r
+ ret ; Direkter Sprung zum Bootloader\r
+.endm\r
+\r
+.macro CHECK_BOOTLOADER_PIN\r
+.endm\r
+\r
tm3d / owSlave2.git / blobdiff