--- /dev/null
+\r
+// Copyright (c) 2017, Tobias Mueller tm(at)tm3d.de\r
+// All rights reserved.\r
+//\r
+// Redistribution and use in source and binary forms, with or without\r
+// modification, are permitted provided that the following conditions are\r
+// met:\r
+//\r
+// * Redistributions of source code must retain the above copyright\r
+// notice, this list of conditions and the following disclaimer.\r
+// * Redistributions in binary form must reproduce the above copyright\r
+// notice, this list of conditions and the following disclaimer in the\r
+// documentation and/or other materials provided with the\r
+// distribution.\r
+// * All advertising materials mentioning features or use of this\r
+// software must display the following acknowledgement: This product\r
+// includes software developed by tm3d.de and its contributors.\r
+// * Neither the name of tm3d.de nor the names of its contributors may\r
+// be used to endorse or promote products derived from this software\r
+// without specific prior written permission.\r
+//\r
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\r
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\r
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\r
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\r
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\r
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\r
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\r
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\r
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+\r
+#define F_CPU 8000000UL\r
+#include <avr/io.h>\r
+#include <avr/interrupt.h>\r
+#include <util/delay.h>\r
+#include <avr/wdt.h>\r
+#include <avr/sleep.h>\r
+#include <avr/pgmspace.h>\r
+\r
+extern void OWINIT();\r
+extern void EXTERN_SLEEP();\r
+\r
+\r
+\r
+uint8_t owid[8]={0x28, 0xA2, 0xD9, 0x84, 0x00, 0x16, 0x02, 0xAC};/**/\r
+uint8_t config_info[26]={0x01,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x02,6,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00};\r
+ \r
+#if (owid>128) \r
+#error "Variable not correct"\r
+#endif\r
+\r
+extern uint8_t mode;\r
+extern uint8_t gcontrol;\r
+extern uint8_t reset_indicator;\r
+extern uint8_t alarmflag;\r
+\r
+\r
+volatile uint8_t wdcounter;\r
+\r
+\r
+typedef union {\r
+ volatile uint8_t bytes[8];\r
+ struct {\r
+ uint16_t temp; //0\r
+ uint8_t TH; //2\r
+ uint8_t TL; //3\r
+ uint8_t config; //4\r
+ uint8_t rrFF; //5\r
+ uint8_t rr00; //6\r
+ uint8_t rr10; //7\r
+ };\r
+} pack_t;\r
+volatile pack_t pack;\r
+\r
+\r
+\r
+\r
+#if defined(__AVR_ATtiny24__)||defined(__AVR_ATtiny44__) || defined(__AVR_ATtiny84__) || defined(__AVR_ATtiny24A__)||defined(__AVR_ATtiny44A__) || defined(__AVR_ATtiny84A__)\r
+ISR(WATCHDOG_vect) {\r
+#else\r
+ISR(WDT_vect) {\r
+#endif \r
+ //sleep_disable(); // Disable Sleep on Wakeup\r
+ wdcounter++;\r
+ if (reset_indicator==1) reset_indicator++;\r
+ else if (reset_indicator==2) mode=0;\r
+/* if (timeout==2) {\r
+ DIS_TIMER;\r
+ EN_OWINT;\r
+ mode=OWM_SLEEP;\r
+ }\r
+ timeout++;*/\r
+ //sleep_enable(); // Enable Sleep Mode\r
+\r
+}\r
+\r
+\r
+volatile double V,ktemp;\r
+\r
+uint16_t ADmess() {\r
+ ADMUX=0b00101100; //3V ADC2+ ADC1- 1x\r
+ ADCSRA|=(1<<ADSC);\r
+ while ((ADCSRA&(1<<ADSC)));\r
+ return ADC;\r
+}\r
+\r
+int main(void){\r
+ //PRR|=(1<<PRUSI)|(1<<PRADC); //Switch off usi and adc for save Power\r
+ pack.temp=0x0550;\r
+ pack.config=0x7F;\r
+ pack.TH=75;\r
+ pack.TL=70;\r
+ pack.rrFF=0xFF;\r
+ pack.rr00=0;\r
+ pack.rr10=0x10;\r
+ PORTA=0xFF-(1<<PINA1)-(1<<PINA2);\r
+ PORTB=0xFF;\r
+ OWINIT();\r
+\r
+ MCUCR &=~(1<<PUD); //All Pins Pullup...\r
+ MCUCR |=(1<<BODS);\r
+\r
+ WDTCSR |= ((1<<WDCE) ); // Enable the WD Change Bit//| (1<<WDE)\r
+ WDTCSR |= (1<<WDIE) | // Enable WDT Interrupt\r
+ (1<<WDP2) | (1<<WDP1); // Set Timeout to ~1 seconds\r
+ MCUSR=0;\r
+ sei();\r
+ ADCSRA=(1<<ADEN)|(1<<ADPS2)|(1<<ADPS1);//|(1<<ADPS0);\r
+ \r
+ \r
+ uint16_t ares[16],sum;\r
+ uint8_t par=0;\r
+ sum=0;\r
+ for(uint8_t i=0;i<16;i++) {\r
+ //sum+=ares[i];\r
+ sum+=ADmess();\r
+ }\r
+ par=0;\r
+ wdcounter=0;\r
+ gcontrol=1;\r
+\r
+ while(1) {\r
+ if (wdcounter>0) {\r
+// ares[par]=ADmess();\r
+ par++;\r
+ if (par>15) par=0;\r
+ wdcounter=0;\r
+ sum=0;\r
+ for(uint8_t i=0;i<16;i++) {\r
+ //sum+=ares[i];\r
+ sum+=ADmess();\r
+ }\r
+\r
+\r
+ }\r
+ if (gcontrol) {\r
+ PORTB|=(1<<PORTB0);\r
+ //V=sum/20.0/1024.0*1.12*1000.0/16.0;\r
+ //V=sum/20.0/1024.0*1.01*1000.0/16.0;\r
+ V=sum/1024.0*182-55*16-16;\r
+ if (V>125*16) V=125*16;\r
+ if (V<-55*16) V=-55*16;\r
+ \r
+ uint16_t htemp=V;\r
+ \r
+ uint8_t t8=pack.temp>>4;\r
+ uint8_t af=0;\r
+ if (t8>pack.TH) af=1;\r
+ if (t8<=pack.TL) af=1;\r
+ cli();\r
+ pack.temp=htemp;\r
+ alarmflag=af;\r
+ sei();\r
+ EXTERN_SLEEP();\r
+ PORTB&=~(1<<PORTB0);\r
+ }\r
+\r
+ \r
+#if defined(__AVR_ATtiny25__)||defined(__AVR_ATtiny45__) || defined(__AVR_ATtiny85__)\r
+ if (((TIMSK & (1<<TOIE0))==0)&& (mode==0))\r
+#endif \r
+#if defined(__AVR_ATtiny24__)||defined(__AVR_ATtiny44__) || defined(__AVR_ATtiny84__) ||defined(__AVR_ATtiny24A__)||defined(__AVR_ATtiny44A__) || defined(__AVR_ATtiny84A__)\r
+ if (((TIMSK0 & (1<<TOIE0))==0)&& (mode==0))\r
+#endif\r
+ {\r
+// CLKPR=(1<<CLKPCE);\r
+ // CLKPR=(1<<CLKPS2); /*0.5Mhz*/\r
+// PORTB&=~(1<<PINB1);\r
+ MCUCR|=(1<<SE)|(1<<SM1);\r
+ MCUCR&=~(1<<ISC01);\r
+ } else {\r
+ MCUCR|=(1<<SE);\r
+ MCUCR&=~(1<<SM1);\r
+ }\r
+ asm("SLEEP");\r
+ }\r
+\r
+\r
+}
\ No newline at end of file
tm3d / owSlave2.git / blobdiff