--- /dev/null
+// Copyright (c) 2017, Tobias Mueller tm(at)tm3d.de\r
+// All rights reserved.\r
+//\r
+// Redistribution and use in source and binary forms, with or without\r
+// modification, are permitted provided that the following conditions are\r
+// met:\r
+//\r
+// * Redistributions of source code must retain the above copyright\r
+// notice, this list of conditions and the following disclaimer.\r
+// * Redistributions in binary form must reproduce the above copyright\r
+// notice, this list of conditions and the following disclaimer in the\r
+// documentation and/or other materials provided with the\r
+// distribution.\r
+// * All advertising materials mentioning features or use of this\r
+// software must display the following acknowledgement: This product\r
+// includes software developed by tm3d.de and its contributors.\r
+// * Neither the name of tm3d.de nor the names of its contributors may\r
+// be used to endorse or promote products derived from this software\r
+// without specific prior written permission.\r
+//\r
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\r
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\r
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\r
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\r
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\r
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\r
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\r
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\r
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+\r
+//!!!!!Max Program size 7551 Byte\r
+#define _CPULLUP_\r
+#define F_CPU 8000000UL\r
+#include <avr/io.h>\r
+#include <avr/interrupt.h>\r
+#include <util/delay.h> \r
+#include <avr/wdt.h>\r
+#include <avr/sleep.h>\r
+#include <avr/pgmspace.h>\r
+#include "../common/owSlave_tools.h"\r
+\r
+\r
+//#define FHEM_PLATINE\r
+#define W1DAQ\r
+//#define JOE_M\r
+volatile uint8_t owid1[8]={0x3A, 0x01, 0xDA, 0x84, 0x00, 0x00, 0x05, 0xA3};/**/\r
+volatile uint8_t owid2[8]={0x3A, 0x02, 0xDA, 0x84, 0x00, 0x00, 0x05, 0xFA};/**/\r
+uint8_t config_info1[26]={0,0,0,0,0,0,0,0,0x02,0,0,0,0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00}; //+2 for CRC\r
+uint8_t config_info2[26]={0,0,0,0,0,0,0,0,0x02,0,0,0,0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00}; //+2 for CRC\r
+ \r
+#if (owid>128) \r
+#error "Variable not correct"\r
+#endif\r
+\r
+OWST_EXTERN_VARS\r
+\r
+uint8_t pin_state1;\r
+uint8_t pin_set1;\r
+uint8_t pin_state2;\r
+uint8_t pin_set2;\r
+\r
+OWST_WDT_ISR\r
+\r
+\r
+#if defined(__AVR_ATtiny44__) || defined(__AVR_ATtiny84__) || defined(__AVR_ATtiny24A__)||defined(__AVR_ATtiny44A__) || defined(__AVR_ATtiny84A__)\r
+#define PCINT_VECTOR PCINT0_vect\r
+#define PIN_REG PINA\r
+#define PIN_DDR DDRA\r
+\r
+#ifdef FHEM_PLATINE\r
+#define PIN_PIOA1 (1<<PINA2)\r
+#define PIN_PIOB1 (1<<PINA1)\r
+#define PIN_PIOA2 (1<<PINA3)\r
+#define PIN_PIOB2 (1<<PINA4)\r
+//LEDS
\r#define LPIN_CH2 (1<<PINB0)
\r#define LDD_CH2 DDRB
\r#define LPORT_CH2 PORTB
\r#define LPIN_CH3 (1<<PINA5)
\r#define LDD_CH3 DDRA
\r#define LPORT_CH3 PORTA
\r#define LPIN_CH0 (1<<PINA7)
\r#define LDD_CH0 DDRA
\r#define LPORT_CH0 PORTA
\r#define LPIN_CH1 (1<<PINB1)
\r#define LDD_CH1 DDRB
\r#define LPORT_CH1 PORTB
\r+\r
+#define LED2_ON LPORT_CH2|=LPIN_CH2;\r
+#endif\r
+\r
+#ifdef JOE_M\r
+#define LED2_ON\r
+#define PIN_PIOA1 (1<<PINA4)\r
+#define PIN_PIOB1 (1<<PINA5)\r
+#define PIN_PIOA2 (1<<PINA6)\r
+#define PIN_PIOB2 (1<<PINA7)\r
+#endif\r
+\r
+#ifdef W1DAQ\r
+#define PIN_PIOB1 (1<<PINA1)\r
+#define PIN_PIOA1 (1<<PINA0)\r
+#define PIN_PIOB2 (1<<PINA7)\r
+#define PIN_PIOA2 (1<<PINA3)\r
+//LEDS
\r#define LPIN_CH0 (1<<PINB1)
\r#define LDD_CH0 DDRB
\r#define LPORT_CH0 PORTB
\r#define LPIN_CH1 (1<<PINB1)
\r#define LDD_CH1 DDRB
\r#define LPORT_CH1 PORTB
\r#define LPIN_CH2 (1<<PINB1)
\r#define LDD_CH2 DDRB
\r#define LPORT_CH2 PORTB
\r#define LPIN_CH3 (1<<PINB1)
\r#define LDD_CH3 DDRB
\r#define LPORT_CH3 PORTB
\r\r+#define LED2_ON LPORT_CH2&=~LPIN_CH2;\r
+#endif\r
+\r
+\r
+\r
+#endif\r
+\r
+\r
+ISR(PCINT0_vect) {\r
+// if (((PIN_REG&PIN_CH2)==0)&&((istat&PIN_CH2)==PIN_CH2)) { counters1.c32[2]++; LED2_ON}\r
+ //if (((PIN_REG&PIN_CH3)==0)&&((istat&PIN_CH3)==PIN_CH3)) { counters1.c32[3]++;LED2_ON }\r
+ if ((PIN_REG&PIN_PIOA1)==0) {pin_state1&=~0x1;LED2_ON} else { pin_state1|=0x01;}\r
+ if ((PIN_REG&PIN_PIOB1)==0) {pin_state1&=~0x4;LED2_ON} else {pin_state1|=0x04;}\r
+ if ((PIN_REG&PIN_PIOA2)==0) {pin_state2&=~0x1;LED2_ON} else {pin_state2|=0x01;}\r
+ if ((PIN_REG&PIN_PIOB2)==0) {pin_state2&=~0x4;LED2_ON} else {pin_state2|=0x04;}\r
+ //Reset Switch on the FHEM_BOARD\r
+ GIFR|=(1<<PCIF0);\r\r\r\r
+}\r
+\r
+\r
+\r
+\r
+\r
+int main(void){\r
+ OWST_INIT_ALL_OFF\r
+ OWINIT();\r
+ \r
+\r
+#if defined(__AVR_ATtiny44__) || defined(__AVR_ATtiny84__) || defined(__AVR_ATtiny24A__)||defined(__AVR_ATtiny44A__) || defined(__AVR_ATtiny84A__)\r
+\r
+ OWST_WDR_CONFIG4\r
+ \r
+#ifndef _CPULLUP_ // pullup\r
+ PORTA&=~(PIN_PIOA1|PIN_PIOB1);\r
+ PORTA&=~(PIN_PIOA2|PIN_PIOB2);\r
+#endif\r
+\r
+#ifdef FHEM_PLATINE //LEDs\r
+ LDD_CH0|=LPIN_CH0;\r LPORT_CH0&=~LPIN_CH0;\r LDD_CH1|=LPIN_CH1;\r LPORT_CH1&=~LPIN_CH1;\r LDD_CH2|=LPIN_CH2;\r LPORT_CH2&=~LPIN_CH2;\r LDD_CH3|=LPIN_CH3;\r LPORT_CH3&=~LPIN_CH3;\r
+#endif\r
+#ifdef W1DAQ\r
+ LDD_CH2|=LPIN_CH2;\r LPORT_CH2&=~LPIN_CH2;\r#endif\r
+\r
+\r
+ GIMSK|=(1<<PCIE0);\r
+ PCMSK0=(PIN_PIOA1|PIN_PIOB1|PIN_PIOA2|PIN_PIOB2); //Nicht ganz korrekt aber die Bits liegen gleich\r
+\r
+ \r
+ \r
+ #endif\r
+ \r
+ OWST_EN_PULLUP\r
+ \r
+ \r
+#ifdef FHEM_PLATINE\r
+\r
+ LPORT_CH0|=LPIN_CH0;\r _delay_ms(500);\r LPORT_CH0&=~LPIN_CH0;\r
+#endif\r
+ pin_set1=0x0F;\r
+ pin_set2=0x0F;\r
+ //pin_state1=0x00;\r
+ //pin_state2=0x00;\r
+ sei();\r
+ while(1) {\r
+\r
+ if (pin_set1&1) {\r
+ DDRA&=~(PIN_PIOA1); //Eingang\r
+ PORTA|=(PIN_PIOA1); //Pullup\r
+ pin_state1|=2;\r
+ } else {\r
+ DDRA|=(PIN_PIOA1); //Ausgang\r
+ PORTA&=~(PIN_PIOA1); //Gegen masse\r
+ pin_state1&=~2;\r
+ }\r
+ if (pin_set1&2) {\r
+ pin_state1|=8;\r
+ DDRA&=~(PIN_PIOB1); //Eingang\r
+ PORTA|=(PIN_PIOB1); //Pullup\r
+ } else {\r
+ DDRA|=(PIN_PIOB1); //Ausgang\r
+ PORTA&=~(PIN_PIOB1); //Gegen masse\r
+ pin_state1&=~8;\r
+ }\r
+ if (pin_set2&1) {\r
+ pin_state2|=2;\r
+ DDRA&=~(PIN_PIOA2); //Eingang\r
+ PORTA|=(PIN_PIOA2); //Pullup\r
+ } else {\r
+ DDRA|=(PIN_PIOA2); //Ausgang\r
+ PORTA&=~(PIN_PIOA2); //Gegen masse\r
+ pin_state2&=~2;\r
+ }\r
+ if (pin_set2&2) {\r
+ DDRA&=~(PIN_PIOB2); //Eingang\r
+ PORTA|=(PIN_PIOB2); //Pullup\r
+ pin_state2|=8;\r
+ } else {\r
+ DDRA|=(PIN_PIOB2); //Ausgang\r
+ PORTA&=~(PIN_PIOB2); //Gegen masse\r
+ pin_state2&=~8;\r
+ }\r
+#ifdef FHEM_PLATINE\r
+ if (LPORT_CH2&LPIN_CH2) {\r _delay_ms(50);\r LPORT_CH2&=~LPIN_CH2;\r }\r
+ if (LPORT_CH1&LPIN_CH1) {\r _delay_ms(50);\r LPORT_CH1&=~LPIN_CH1;\r }\r
+#endif\r
+#ifdef W1DAQ\r
+ if ((LPORT_CH2&LPIN_CH2)==0) {\r _delay_ms(50);\r LPORT_CH2|=LPIN_CH2;\r }\r
+#endif\r
+ OWST_MAIN_END \r
+ }\r
+\r
+\r
+}\r
+\r
tm3d / owSlave2.git / blobdiff