--- /dev/null
+// Copyright (c) 2017, Tobias Mueller tm(at)tm3d.de\r
+// All rights reserved.\r
+//\r
+// Redistribution and use in source and binary forms, with or without\r
+// modification, are permitted provided that the following conditions are\r
+// met:\r
+//\r
+// * Redistributions of source code must retain the above copyright\r
+// notice, this list of conditions and the following disclaimer.\r
+// * Redistributions in binary form must reproduce the above copyright\r
+// notice, this list of conditions and the following disclaimer in the\r
+// documentation and/or other materials provided with the\r
+// distribution.\r
+// * All advertising materials mentioning features or use of this\r
+// software must display the following acknowledgement: This product\r
+// includes software developed by tm3d.de and its contributors.\r
+// * Neither the name of tm3d.de nor the names of its contributors may\r
+// be used to endorse or promote products derived from this software\r
+// without specific prior written permission.\r
+//\r
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\r
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\r
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\r
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\r
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\r
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\r
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\r
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\r
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+\r
+#define _CPULLUP_\r
+\r
+#define F_CPU 8000000UL\r
+#include <avr/io.h>\r
+#include <avr/interrupt.h>\r
+#include <util/delay.h>\r
+#include <avr/wdt.h>\r
+#include <avr/sleep.h>\r
+\r
+\r
+\r
+extern void OWINIT();\r
+\r
+uint8_t owid[8]={0x1D, 0xA2, 0xD9, 0x84, 0x00, 0x26, 0x02, 0x5C};/**/\r
+uint8_t config_info[26]={9,13,9,13,9,13,9,13,0x02,19,19,19,19,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00}; //+2 for CRC\r
+\r
+ \r
+\r
+extern uint8_t mode;\r
+extern uint8_t gcontrol;\r
+extern uint8_t reset_indicator;\r
+\r
+\r
+\r
+\r
+\r
+\r
+typedef union {\r
+ volatile uint8_t bytes[45];\r
+ struct {\r
+ uint16_t addr;\r
+ uint8_t status;\r
+ uint8_t scratch[32];//3\r
+ uint32_t counter; //35\r
+ uint32_t zero; //39\r
+ uint16_t crc; //43\r
+ };\r
+} counterpack_t;\r
+counterpack_t pack;\r
+\r
+volatile uint8_t lastcps;\r
+typedef union {\r
+ uint32_t c32[4];\r
+ uint8_t c8[16];\r
+} counters_t;\r
+\r
+volatile counters_t counters;\r
+\r
+volatile uint8_t istat;\r
+volatile uint8_t changefromeeprom;\r
+\r
+\r
+\r
+#if defined(__AVR_ATtiny24__)||defined(__AVR_ATtiny44__) || defined(__AVR_ATtiny84__) || defined(__AVR_ATtiny24A__)||defined(__AVR_ATtiny44A__) || defined(__AVR_ATtiny84A__)\r
+#define PCINT_VECTOR PCINT0_vect\r
+#define PIN_REG PINA\r
+#define PIN_DDR DDRA\r
+#define PIN_CH2 (1<<PINA4)\r
+#define PIN_CH3 (1<<PINA5)\r
+#define PIN_CH0 (1<<PINA6)\r
+#define PIN_CH1 (1<<PINA7)\r
+#define PORT_EE PINA //WARNING have to be the same PORT like PINREG because of istat\r
+#define PIN_EE (1<<PINA0)\r
+#define TEST_TIMER ((TIMSK0 & (1<<TOIE0))==0)\r
+\r
+#endif\r
+\r
+\r
+ISR(PCINT0_vect) {\r
+ if (((PIN_REG&PIN_CH2)==0)&&((istat&PIN_CH2)==PIN_CH2)) { counters.c32[2]++; }\r
+ if (((PIN_REG&PIN_CH3)==0)&&((istat&PIN_CH3)==PIN_CH3)) { counters.c32[3]++; }\r
+ if (((PIN_REG&PIN_CH0)==0)&&((istat&PIN_CH0)==PIN_CH0)) { counters.c32[0]++; }\r
+ if (((PIN_REG&PIN_CH1)==0)&&((istat&PIN_CH1)==PIN_CH1)) { counters.c32[1]++; }\r
+ istat=PIN_REG;\r
+ changefromeeprom=1;\r
+}\r
+\r
+\r
+ISR(ANA_COMP_vect) {\r
+ if (changefromeeprom==0) return;\r
+ if ((ACSR&(1<<ACO))!=0) {\r
+ _delay_ms(5);\r
+ if ((ACSR&(1<<ACO))!=0) {\r
+ CLKPR=0x80;//Switch to 4 MHz \r
+ CLKPR=01; \r
+ \r
+ PORTB|=(1<<PINB1);\r
+ EEARH=0;\r
+ for(uint8_t i=0;i<16;i++) {\r
+ uint8_t addr=i^0x0C;\r
+ while(EECR & (1<<EEPE));\r
+ EECR = (0<<EEPM1)|(0<<EEPM0);\r
+ EEARL = i;\r
+ EEDR = counters.c8[addr];\r
+ EECR |= (1<<EEMPE);\r
+ EECR |= (1<<EEPE);\r
+ }\r
+ changefromeeprom=0;\r
+ PORTB&=~(1<<PINB1);\r
+ CLKPR=0x80;\r
+ CLKPR=0;\r
+ GIFR|=(1<<INTF0);\r
+ }\r
+ }\r
+ \r
+}\r
+\r
+int testSW(void) {\r
+ uint8_t r;\r
+ DDRB&=~(1<<PORTB0); //Eingang\r
+ __asm__ __volatile__ ("nop");\r
+ PORTB|=(1<<PORTB0); //Pullup\r
+ __asm__ __volatile__ ("nop");\r
+ __asm__ __volatile__ ("nop");\r
+ __asm__ __volatile__ ("nop");\r
+ __asm__ __volatile__ ("nop");\r
+ __asm__ __volatile__ ("nop");\r
+ r=PINB&(1<<PORTB0);\r
+ __asm__ __volatile__ ("nop");\r
+ PORTB&=~(1<<PORTB0);\r
+ __asm__ __volatile__ ("nop");\r
+ DDRB|=(1<<PORTB0); //Eingang\r
+ return (r==0);\r
+ \r
+ \r
+}\r
+\r
+\r
+int main(void){\r
+ PRR|=(1<<PRUSI)|(1<<PRADC); //Switch off usi and adc for save Power\r
+ OWINIT();\r
+ \r
+ pack.zero=0;\r
+ counters.c32[0]=0;\r
+ counters.c32[2]=0;\r
+ counters.c32[1]=0;\r
+ counters.c32[3]=0;\r
+ changefromeeprom=1;\r
+ ACSR|=(1<<ACD); //Disable Comparator\r
+ ADCSRB|=(1<<ACME); //Disable Analog multiplexer\r
+ MCUCR &=~(1<<PUD); //All Pins Pullup...\r
+ \r
+#if defined(__AVR_ATtiny24__)||defined(__AVR_ATtiny44__) || defined(__AVR_ATtiny84__) || defined(__AVR_ATtiny24A__)||defined(__AVR_ATtiny44A__) || defined(__AVR_ATtiny84A__)\r
+\r
+ PORTB|=0xFF-(1<<PINB2); //Make PullUp an all Pins but not OW_PIN\r
+ PORTA|=0xFF;\r
+ PORTA&=~(1<<PINA2); //AIN1 \r
+#ifndef _CPULLUP_\r
+ PORTA&=~((1<<PINA4)|(1<<PINA5));\r
+ PORTA&=~((1<<PINA6)|(1<<PINA7));\r
+ #endif\r
+\r
+ GIMSK|=(1<<PCIE0);\r
+ PCMSK0=(1<<PCINT4)|(1<<PCINT5)\r
+ |(1<<PCINT6)|(1<<PCINT7);\r
+ \r
+ \r
+ istat=PINB;\r
+#endif\r
+\r
+ EEARH=0;\r
+ \r
+ uint8_t addr;\r
+ \r
+ if (testSW()) { //Jumper gesetzt ->Ruecksetzen\r
+ for(uint8_t i=0;i<16;i++) {\r
+ while(EECR & (1<<EEPE));\r
+ EECR = (0<<EEPM1)|(0<<EEPM0);\r
+ EEARL = i;\r
+ EEDR = 0;\r
+ EECR |= (1<<EEMPE);\r
+ EECR |= (1<<EEPE);\r
+ } \r
+ } \r
+ \r
+ \r
+ for(uint8_t i=0;i<16;i++) {\r
+ addr=i^0x0C;\r
+ while(EECR & (1<<EEPE)); \r
+ EEARL=i;\r
+ EECR |= (1<<EERE);\r
+ counters.c8[addr]=EEDR;\r
+ }\r
+ changefromeeprom=0; //Daten neu eingelesen\r
+ for (uint8_t i=0;i<4;i++) {\r
+ if (counters.c32[i]==0xFFFFFFFF) {\r
+ counters.c32[i]=0;\r
+ changefromeeprom=1; //Daten geaendert\r
+ }\r
+ //counters.c32[i]=0;\r
+ }\r
+ \r
+\r
+ /*for(uint8_t i=0;i<16;i++) {\r
+ while(EECR & (1<<EEPE));\r
+ EECR = (1<<EEPM0);\r
+ EEARL = i;\r
+ EECR |= (1<<EEMPE);\r
+ EECR |= (1<<EEPE);\r
+ }*/\r
+ \r
+ \r
+\r
+\r
+ DIDR0|=(1<<ADC2D)|(1<<ADC1D); // Disable Digital input on Analog AIN0/AIN1 (PINA1 / PINA2)\r
+ ACSR&=~(1<<ACD);\r
+ ACSR|=(1<<ACIE)|(1<<ACIS1)|(1<<ACIS0)|(1<<ACBG); //Enabble comperator interrupt Rising edge....(1<<ACIS0)\r
+\r
+ sei();\r
+ DDRB|=(1<<PINB1);\r
+ PORTB&=~(1<<PINB1);\r
+ while(1) {\r
+ \r
+ MCUCR|=(1<<SE);\r
+ MCUCR&=~(1<<SM1); \r
+ asm("SLEEP");\r
+ }\r
+}
\ No newline at end of file
tm3d / owSlave2.git / blobdiff