--- /dev/null
+// Copyright (c) 2017, Tobias Mueller tm(at)tm3d.de\r
+// All rights reserved.\r
+//\r
+// Redistribution and use in source and binary forms, with or without\r
+// modification, are permitted provided that the following conditions are\r
+// met:\r
+//\r
+// * Redistributions of source code must retain the above copyright\r
+// notice, this list of conditions and the following disclaimer.\r
+// * Redistributions in binary form must reproduce the above copyright\r
+// notice, this list of conditions and the following disclaimer in the\r
+// documentation and/or other materials provided with the\r
+// distribution.\r
+// * All advertising materials mentioning features or use of this\r
+// software must display the following acknowledgement: This product\r
+// includes software developed by tm3d.de and its contributors.\r
+// * Neither the name of tm3d.de nor the names of its contributors may\r
+// be used to endorse or promote products derived from this software\r
+// without specific prior written permission.\r
+//\r
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\r
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\r
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\r
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\r
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\r
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\r
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\r
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\r
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+\r
+//!!!!!Max Program size 7551 Byte\r
+#define _CPULLUP_\r
+#define F_CPU 8000000UL\r
+#include <avr/io.h>\r
+#include <avr/interrupt.h>\r
+#include <util/delay.h> \r
+#include <avr/wdt.h>\r
+#include <avr/sleep.h>\r
+#include <avr/pgmspace.h>\r
+\r
+extern void OWINIT(void);\r
+extern void EXTERN_SLEEP(void);\r
+#define FHEM_PLATINE\r
+\r
+volatile uint8_t owid1[8]={0x1D, 0x1D, 0xDA, 0x84, 0x00, 0x00, 0x05, 0xD9};/**/\r
+volatile uint8_t owid2[8]={0x3A, 0x3A, 0xDA, 0x84, 0x00, 0x00, 0x05, 0xB6};/**/\r
+uint8_t config_info1[26]={9,13,9,13,9,13,9,13,0x02,19,19,19,19,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00}; //+2 for CRC\r
+uint8_t config_info2[26]={0,0,0,0,0,0,0,0,0x02,0,0,0,0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00}; //+2 for CRC\r
+ \r
+#if (owid>128) \r
+#error "Variable not correct"\r
+#endif\r
+\r
+extern uint8_t mode;\r
+extern uint8_t gcontrol;\r
+extern uint8_t reset_indicator;\r
+\r
+\r
+uint8_t pin_state;\r
+uint8_t pin_set;\r
+\r
+\r
+typedef union {\r
+ volatile uint8_t bytes[45];\r
+ struct {\r
+ uint16_t addr;\r
+ uint8_t status;\r
+ uint8_t scratch[32];//3\r
+ uint32_t counter; //35\r
+ uint32_t zero; //39\r
+ uint16_t crc; //43\r
+ };\r
+} counterpack_t;\r
+counterpack_t pack1;\r
+\r
+\r
+\r
+volatile uint8_t lastcps;\r
+typedef union {\r
+ uint32_t c32[4];\r
+ uint8_t c8[16];\r
+} counters_t;\r
+\r
+volatile counters_t counters1;\r
+\r
+\r
+volatile uint8_t istat;\r
+volatile uint8_t changefromeeprom;\r
+\r
+#if defined(__AVR_ATtiny44__) || defined(__AVR_ATtiny84__) || defined(__AVR_ATtiny24A__)||defined(__AVR_ATtiny44A__) || defined(__AVR_ATtiny84A__)\r
+#define PCINT_VECTOR PCINT0_vect\r
+#define PIN_REG PINA\r
+#define PIN_DDR DDRA\r
+\r
+#ifdef FHEM_PLATINE\r
+#define PIN_CH3 (1<<PINA2)\r
+#define PIN_CH2 (1<<PINA1)\r
+#define PIN_PIOA (1<<PINA3)\r
+#define PIN_PIOB (1<<PINA4)\r
+//LEDS
\r#define LPIN_CH2 (1<<PINB0)
\r#define LDD_CH2 DDRB
\r#define LPORT_CH2 PORTB
\r#define LPIN_CH3 (1<<PINA5)
\r#define LDD_CH3 DDRA
\r#define LPORT_CH3 PORTA
\r#define LPIN_CH0 (1<<PINA7)
\r#define LDD_CH0 DDRA
\r#define LPORT_CH0 PORTA
\r#define LPIN_CH1 (1<<PINB1)
\r#define LDD_CH1 DDRB
\r#define LPORT_CH1 PORTB
\r+\r
+#define LED2_ON LPORT_CH2|=LPIN_CH2;\r
+#else\r
+#define LED2_ON\r
+#define PIN_CH2 (1<<PINA4)\r
+#define PIN_CH3 (1<<PINA5)\r
+#define PIN_PIOA (1<<PINA6)\r
+#define PIN_PIOB (1<<PINA7)\r
+#endif\r
+\r
+#define TEST_TIMER ((TIMSK0 & (1<<TOIE0))==0)\r
+\r
+\r
+#endif\r
+\r
+\r
+ISR(PCINT0_vect) {\r
+ if (((PIN_REG&PIN_CH2)==0)&&((istat&PIN_CH2)==PIN_CH2)) { counters1.c32[2]++; }\r
+ if (((PIN_REG&PIN_CH3)==0)&&((istat&PIN_CH3)==PIN_CH3)) { counters1.c32[3]++; }\r
+ if ((PIN_REG&PIN_PIOA)==0) pin_state&=~0x1; else pin_state|=0x01;\r
+ if ((PIN_REG&PIN_PIOB)==0) pin_state&=~0x4; else pin_state|=0x04;\r
+ //Reset Switch on the FHEM_BOARD\r
+ #ifdef FHEM_PLATINE //clear counter\r
+ if ((((PINA&(1<<PINA6)))==0)&&((istat&(1<<PINA6))==(1<<PINA6))) {
\r _delay_ms(100);
\r if (((PINA&(1<<PINA6)))==0) {
\r LPORT_CH3|=LPIN_CH3;
\r _delay_ms(100);
\r counters1.c32[2]=0;
\r counters1.c32[3]=0;
\r //count Resets
\r counters1.c32[0]++;
\r LPORT_CH3&=~LPIN_CH3;
\r }
\r GIFR|=(1<<PCIF0);
\r }
\r #endif
\r\r+ istat=PIN_REG;\r
+ changefromeeprom=1;\r
+}\r
+\r
+\r
+ISR(ANA_COMP_vect) {\r
+ if (changefromeeprom==0) return;\r
+ if ((ACSR&(1<<ACO))!=0) {\r
+ _delay_ms(5);\r
+ if ((ACSR&(1<<ACO))!=0) {\r
+ counters1.c32[1]++;\r CLKPR=0x80;//Switch to 4 MHz\r
+ CLKPR=01;\r
+ \r
+ PORTB|=(1<<PINB1);\r
+ EEARH=0;\r
+ for(uint8_t i=0;i<16;i++) {\r
+ uint8_t addr=i;\r
+ while(EECR & (1<<EEPE));\r
+ EECR = (0<<EEPM1)|(0<<EEPM0);\r
+ EEARL = i;\r
+ EEDR = counters1.c8[addr];\r
+ EECR |= (1<<EEMPE);\r
+ EECR |= (1<<EEPE);\r
+ }\r
+ changefromeeprom=0;\r
+ PORTB&=~(1<<PINB1);\r
+ CLKPR=0x80;\r
+ CLKPR=0;\r
+ GIFR|=(1<<INTF0);\r
+ }\r
+ }\r
+ \r
+}\r
+\r
+\r
+int main(void){\r
+ #ifdef FHEM_PLATINE\r
+ PRR|=(1<<PRUSI); //Switch off usi, dont switch of ADC cause Multiplexer is used for the correct AIN1 pin\r
+ #else\r
+ PRR|=(1<<PRUSI)|(1<<PRADC); //Switch off usi and adc for save Power\r
+ #endif\r
+ OWINIT();\r
+ \r
+ pack1.zero=0;\r
+ counters1.c32[0]=0;\r
+ counters1.c32[2]=0;\r
+ counters1.c32[1]=0;\r
+ counters1.c32[3]=0;\r
+ \r
+ changefromeeprom=1;\r
+ #if defined(__AVR_ATtiny44__) || defined(__AVR_ATtiny84__) || defined(__AVR_ATtiny24A__)||defined(__AVR_ATtiny44A__) || defined(__AVR_ATtiny84A__)\r
+\r
+ PORTB|=0xFF-(1<<PINB2); //Make PullUp an all Pins but not OW_PIN\r
+ PORTA|=0xFF;\r
+\r
+ #ifndef _CPULLUP_ // pullup\r
+ PORTA&=~(PIN_PIOA|PIN_PIOB);\r
+ PORTA&=~(PIN_CH2|PIN_CH3);\r
+ #endif\r
+\r
+ #ifdef FHEM_PLATINE //LEDs\r
+ LDD_CH0|=LPIN_CH0;\r LPORT_CH0&=~LPIN_CH0;\r LDD_CH1|=LPIN_CH1;\r LPORT_CH1&=~LPIN_CH1;\r LDD_CH2|=LPIN_CH2;\r LPORT_CH2&=~LPIN_CH2;\r LDD_CH3|=LPIN_CH3;\r LPORT_CH3&=~LPIN_CH3;\r
+ #endif\r
+\r
+ GIMSK|=(1<<PCIE0);\r
+ PCMSK0=(PIN_PIOA|PIN_PIOB|PIN_CH2|PIN_CH3); //Nicht ganz korrekt aber die Bits liegen gleich\r
+\r
+ \r
+ \r
+ istat=PINA;\r
+ #endif\r
+\r
+ EEARH=0;\r
+ uint8_t addr;\r
+ for(uint8_t i=0;i<16;i++) {\r
+ addr=i;\r
+ while(EECR & (1<<EEPE));\r
+ EEARL=i;\r
+ EECR |= (1<<EERE);\r
+ counters1.c8[addr]=EEDR;\r
+ }\r
+ changefromeeprom=0; //Daten neu eingelesen\r
+ for (uint8_t i=0;i<4;i++) {\r
+ if (counters1.c32[i]==0xFFFFFFFF) {\r
+ counters1.c32[i]=0;\r
+ changefromeeprom=1; //Daten geaendert\r
+ }\r
+ //counters.c32[i]=0;\r
+ }\r
+\r
+ //ACSR|=(1<<ACD); //Disable Comparator\r
+ ADCSRB|=(1<<ACME); //Disable Analog multiplexer\r
+ MCUCR &=~(1<<PUD); //All Pins Pullup...\r
+#ifdef FHEM_PLATINE\r
+ DIDR0|=(1<<ADC0D);\r
+ PORTA&=~(1<<PINA0);//Disable Pullup\r
+#else\r
+ DIDR0|=(1<<ADC2D)|(1<<ADC1D); // Disable Digital input on Analog AIN0/AIN1 (PINA1 / PINA2)\r
+ PORTA&=~(1<<PINA2); //AIN1\r
+#endif\r
+ ACSR&=~(1<<ACD);\r
+ ACSR|=(1<<ACIE)|(1<<ACIS1)|(1<<ACIS0)|(1<<ACBG); //Enabble comperator interrupt Rising edge....(1<<ACIS0) -> minus of Comperator falls down -> output of Comperator rises\r
+#ifdef FHEM_PLATINE\r
+ //Switch std AIN1 to A0\r
+ ADCSRA&=~(1<<ADEN);\r
+ ADCSRB=(1<<ACME);\r
+ ADMUX=0;\r
+ //Taster\r
+ DDRA&=~(1<<PINA6);
\r PCMSK0|=(1<<PCINT6);
\r PORTA|=(1<<PINA6); //Pullup
\r+\r
+\r
+ LPORT_CH0|=LPIN_CH0;\r _delay_ms(500);\r LPORT_CH0&=~LPIN_CH0;\r
+#endif\r
+ pin_state=0x0F;\r
+ sei();\r
+ while(1) {\r
+\r
+ if (pin_set&1) {\r
+ counters1.c32[3]=0;\r
+ pin_set&=~1;\r
+ changefromeeprom=1;\r
+ }\r
+ if (pin_set&2) {\r
+ counters1.c32[2]=0;\r
+ pin_set&=~2;\r
+ changefromeeprom=1;\r
+ }\r
+ /*if (counters1.c32[2]==0) {\r
+ pin_state|=2;\r
+ } else pin_state&=~2;\r
+ if (counters1.c32[3]==0) {\r
+ pin_state|=8;\r
+ } else pin_state&=~8;*/\r
+\r
+#ifdef FHEM_PLATINE\r
+ if (LPORT_CH2&LPIN_CH2) {\r _delay_ms(50);\r LPORT_CH2&=~LPIN_CH2;\r }\r
+#endif\r
+#ifndef FHEM_PLATINE\r
+ if ((PINB&(1<<PORTB0))==0) { //Jumper gesetzt ->Ruecksetzen\r
+ for (uint8_t i=2;i<4;i++) {\r
+ counters1.c32[i]=0;\r
+ }\r
+ //count Resets\r counters1.c32[0]++;\r changefromeeprom=1;\r
+ }\r
+#endif\r
+ MCUCR|=(1<<SE);\r
+ MCUCR&=~(1<<SM1);\r
+ asm("SLEEP");\r
+ }\r
+\r
+\r
+}\r
+\r
tm3d / owSlave2.git / blobdiff