--- /dev/null
+\r
+// Copyright (c) 2017, Tobias Mueller tm(at)tm3d.de\r
+// All rights reserved.\r
+//\r
+// Redistribution and use in source and binary forms, with or without\r
+// modification, are permitted provided that the following conditions are\r
+// met:\r
+//\r
+// * Redistributions of source code must retain the above copyright\r
+// notice, this list of conditions and the following disclaimer.\r
+// * Redistributions in binary form must reproduce the above copyright\r
+// notice, this list of conditions and the following disclaimer in the\r
+// documentation and/or other materials provided with the\r
+// distribution.\r
+// * All advertising materials mentioning features or use of this\r
+// software must display the following acknowledgement: This product\r
+// includes software developed by tm3d.de and its contributors.\r
+// * Neither the name of tm3d.de nor the names of its contributors may\r
+// be used to endorse or promote products derived from this software\r
+// without specific prior written permission.\r
+//\r
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\r
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\r
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\r
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\r
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\r
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\r
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\r
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\r
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+\r
+#define F_CPU 8000000UL\r
+#include <avr/io.h>\r
+#include <avr/interrupt.h>\r
+#include <util/delay.h>\r
+#include <avr/wdt.h>\r
+#include <avr/sleep.h>\r
+#include <avr/pgmspace.h>\r
+#include "../common/I2C/TWI_Master.h"\r
+#include "../common/I2C/BME680.h"\r
+\r
+extern void OWINIT();\r
+extern void EXTERN_SLEEP();\r
+\r
+uint8_t owid[8]={0x20, 0xA2, 0xD9, 0x84, 0x00, 0x16, 0x23, 0x20};/**/\r
+//uint8_t config_info[26]={0x03,13,0x03,13,0x03,13,0x3,15,0x02,20,20,20,20,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00};\r
+//uint8_t config_info[26]={1,14,4,8,2,8,11,18,0x02,24,24,24,24,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00};\r
+uint8_t config_info[26]={1,13,4,13,2,8,11,8,0x02,24,24,24,24,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00};\r
+\r
+\r
+#if (owid>128) \r
+#error "Variable not correct"\r
+#endif\r
+\r
+extern uint8_t mode;\r
+extern uint8_t gcontrol;\r
+extern uint8_t reset_indicator;\r
+extern uint8_t alarmflag;\r
+volatile uint8_t wdcounter=10;\r
+\r
+\r
+#if defined(__AVR_ATtiny24__)||defined(__AVR_ATtiny44__) || defined(__AVR_ATtiny84__) || defined(__AVR_ATtiny24A__)||defined(__AVR_ATtiny44A__) || defined(__AVR_ATtiny84A__)\r
+ISR(WATCHDOG_vect) {\r
+ #else\r
+ ISR(WDT_vect) {\r
+ #endif\r
+ wdcounter++;\r
+ // if (reset_indicator==1) reset_indicator++;\r
+ //else if (reset_indicator==2) mode=0;\r
+ }\r
+\r
+typedef union {\r
+ volatile uint8_t bytes[0x22];\r
+ struct {\r
+ //Page0\r
+ uint16_t A; //0\r
+ uint16_t B; //2\r
+ uint16_t C; //4\r
+ uint16_t D; //6\r
+ //Page1\r
+ uint8_t CSA1;\r
+ uint8_t CSA2;\r
+ uint8_t CSB1;\r
+ uint8_t CSB2;\r
+ uint8_t CSC1;\r
+ uint8_t CSC2;\r
+ uint8_t CSD1;\r
+ uint8_t CSD2;\r
+ //Page2\r
+ uint8_t LA;\r
+ uint8_t HA;\r
+ uint8_t LB;\r
+ uint8_t HB;\r
+ uint8_t LC;\r
+ uint8_t HC;\r
+ uint8_t LD;\r
+ uint8_t HD;\r
+ //Page3\r
+ uint8_t FC1;\r
+ uint8_t FC2;\r
+ uint8_t FC3;\r
+ uint8_t FC4;\r
+ uint8_t VCCP;\r
+ uint8_t FC5;\r
+ uint8_t FC6;\r
+ uint8_t FC7;\r
+ uint8_t convc1;\r
+ uint8_t convc2;\r
+ \r
+ \r
+ };\r
+} pack_t;\r
+volatile pack_t pack;\r
+\r
+\r
+int16_t T;\r
+uint16_t H;\r
+uint32_t P;\r
+uint16_t G;\r
+\r
+\r
+int main(void){\r
+ pack.A=0;\r
+ pack.B=0;\r
+ pack.C=0;\r
+ pack.D=0;\r
+ pack.CSA1=0x08;\r
+ pack.CSA2=0x8C;\r
+ pack.CSB1=0x08;\r
+ pack.CSB2=0x8C;\r
+ pack.CSC1=0x08;\r
+ pack.CSC2=0x8C;\r
+ pack.CSD1=0x08;\r
+ pack.CSD2=0x8C;\r
+ pack.HA=0xFF;\r
+ pack.LA=0x00;\r
+ pack.HB=0xFF;\r
+ pack.LB=0x00;\r
+ pack.HC=0xFF;\r
+ pack.LC=0x00;\r
+ pack.HD=0xFF;\r
+ pack.LD=0x00;\r
+ pack.VCCP=0;\r
+\r
+ PORTA=0xFF;\r
+ //PORTB=0xFF;\r
+ //PORTC=0xFF;\r
+// PORTD=0xFF;\r
+\r
+ OWINIT();\r
+\r
+ MCUCR &=~(1<<PUD); //All Pins Pullup...\r
+ MCUCR |=(1<<BODS);\r
+\r
+ //PORTA&=~((1<<PINA0)|(1<<PINA1)|(1<<PINA2)|(1<<PINA3));\r
+\r
+\r
+\r
+ WDTCSR |= (1<<WDCE) |(1<<WDE); // Enable the WD Change Bit//| (1<<WDE)\r
+ WDTCSR = (1<<WDIE) | // Enable WDT Interrupt\r
+ (1<<WDP3) | (1<<WDP0); // Set Timeout to ~8 seconds\r
+\r
+ wdcounter=4;\r
+ \r
+ gcontrol=1;\r
+ TWI_Master_Initialise();\r
+ \r
+ initBME680();\r
+ sei();\r
+ \r
+ //DDRB|=(1<<PINB1);\r
+\r
+ while(1) {\r
+ if (wdcounter>1) {\r
+ readBMP680(&T,&H,&P,&G);\r
+ wdcounter=0;\r
+ }\r
+\r
+ if (gcontrol) {\r
+ //PORTB|=(1<<PINB1);\r
+ uint8_t bb=1;\r
+ uint8_t bb1=1;\r
+ for(uint8_t i=0;i<4;i++){\r
+ if (pack.convc1&bb1) {\r
+ if (pack.convc2&(bb)) {pack.bytes[i*2]=0;pack.bytes[i*2+1]=0;}\r
+ bb=bb<<1;\r
+ if (pack.convc2&(bb)) {pack.bytes[i*2]=0xFF;pack.bytes[i*2+1]=0xFF;}\r
+ bb=bb<<1;\r
+ } else bb=bb<<2;\r
+ bb1=bb1<<1; \r
+ }\r
+ //CHanel A\r
+ if (pack.convc1&1) {\r
+ \r
+ //cli();pack.A=rlight[0];sei();\r
+ //cli();pack.A=r_gain;sei();\r
+ //cli();pack.A=T+32767;sei();\r
+ cli();pack.A=T;sei();\r
+ alarmflag=0;\r
+ if (pack.CSA2&0x08) //AEH\r
+ if (pack.bytes[1]>pack.HA) {alarmflag=1;pack.CSA2|=0x20;}\r
+ if (pack.CSA2&0x04) //AEL\r
+ if (pack.bytes[1]<pack.LA) {alarmflag=1;pack.CSA2|=0x10;}\r
+ }\r
+\r
+ if (pack.convc1&2) {\r
+ //cli();pack.B=rlight[1];sei();\r
+ //cli();pack.B=atime;sei();\r
+ cli();pack.B=H;sei();\r
+ if (pack.CSB2&0x08) //AEH\r
+ if (pack.bytes[1]>pack.HB) {alarmflag=1;pack.CSB2|=0x20;}\r
+ if (pack.CSB2&0x04) //AEL\r
+ if (pack.bytes[1]<pack.LB) {alarmflag=1;pack.CSB2|=0x10;}\r
+ }\r
+\r
+ if (pack.convc1&4) {\r
+ //cli();pack.C=rlight[2];sei();\r
+ cli();pack.C=P/10;sei();\r
+ if (pack.CSC2&0x08) //AEH\r
+ if (pack.bytes[1]>pack.HC) {alarmflag=1;pack.CSC2|=0x20;}\r
+ if (pack.CSC2&0x04) //AEL\r
+ if (pack.bytes[1]<pack.LC) {alarmflag=1;pack.CSC2|=0x10;}\r
+ } \r
+ if (pack.convc1&8) {\r
+ //cli();pack.D=rlight[3];sei();\r
+ cli();pack.D=G;sei();\r
+ if (pack.CSD2&0x08) //AEH\r
+ if (pack.bytes[1]>pack.HD) {alarmflag=1;pack.CSD2|=0x20;}\r
+ if (pack.CSD2&0x04) //AEL\r
+ if (pack.bytes[1]<pack.LD) {alarmflag=1;pack.CSD2|=0x10;}\r
+ }\r
+ \r
+ EXTERN_SLEEP();\r
+ //PORTB&=~(1<<PINB1);\r
+ }\r
+\r
+ uint8_t bb=1;\r
+ for(uint8_t i=0;i<4;i++) {\r
+ if (pack.bytes[8+i*2]&0x80) { //Chanel as output\r
+ if (pack.bytes[8+i*2]&0x40) {\r
+ //DDRA|=bb;\r
+ } else {\r
+ //DDRA&=~bb;\r
+ }\r
+ } else {\r
+ //DDRA&=~bb;\r
+ }\r
+ bb=bb*2;\r
+ }\r
+ \r
+#if defined(__AVR_ATtiny25__)||defined(__AVR_ATtiny45__) || defined(__AVR_ATtiny85__)\r
+ if (((TIMSK & (1<<TOIE0))==0)&& (mode==0))\r
+#endif \r
+#if defined(__AVR_ATtiny24__)||defined(__AVR_ATtiny44__) || defined(__AVR_ATtiny84__) ||defined(__AVR_ATtiny24A__)||defined(__AVR_ATtiny44A__) || defined(__AVR_ATtiny84A__) ||defined(__AVR_ATmega168__)||defined(__AVR_ATmega168A__) ||defined(__AVR_ATmega328__) ||defined(__AVR_ATmega328P__) ||defined(__AVR_ATmega328PB__)\r
+\r
+ if (((TIMSK0 & (1<<TOIE0))==0)&& (mode==0))\r
+#endif\r
+ {\r
+\r
+ MCUCR|=(1<<SE)|(1<<SM1);\r
+ MCUCR&=~(1<<ISC01);\r
+ } else {\r
+ MCUCR|=(1<<SE);\r
+ MCUCR&=~(1<<SM1);\r
+ }\r
+ asm("SLEEP");\r
+ }\r
+\r
+\r
+}
\ No newline at end of file
tm3d / owSlave2.git / blobdiff