--- /dev/null
+\r
+// Copyright (c) 2018, Tobias Mueller tm(at)tm3d.de\r
+// All rights reserved. \r
+// \r
+// Redistribution and use in source and binary forms, with or without \r
+// modification, are permitted provided that the following conditions are \r
+// met: \r
+// \r
+// * Redistributions of source code must retain the above copyright \r
+// notice, this list of conditions and the following disclaimer. \r
+// * Redistributions in binary form must reproduce the above copyright \r
+// notice, this list of conditions and the following disclaimer in the \r
+// documentation and/or other materials provided with the \r
+// distribution. \r
+// * All advertising materials mentioning features or use of this \r
+// software must display the following acknowledgement: This product \r
+// includes software developed by tm3d.de and its contributors. \r
+// * Neither the name of tm3d.de nor the names of its contributors may \r
+// be used to endorse or promote products derived from this software \r
+// without specific prior written permission. \r
+// \r
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \r
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT \r
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR \r
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT \r
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, \r
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT \r
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, \r
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY \r
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT \r
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE \r
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. \r
+\r
+#define _CHANGEABLE_ID_\r
+#define _ZERO_POLLING_\r
+#define _HANDLE_CC_COMMAND_\r
+#include "../common/OWConfig.s"\r
+#include "../common/OWCRC8_16.s"\r
+\r
+.extern pack1,8\r
+\r
+.extern pack2,8\r
+.comm addr,1 ;zweites Adressbyte ist unnoetig (Warum auch immer fuer 32 Byte 16 Bit Adressen verwendet werden....)\r
+.comm crcsave,1 ; zwischenspeicherspeicher fuer crc nur zweites byte....\r
+//.extern am2302_temp,2\r
+.comm stat_to_sample,1\r
+\r
+.comm block,1 ; Block der augegeben, geschrieben wird (Parameter von READ/WRITE Scratchpad)\r
+.comm cpsp,1 ; Copy Scratchpad marker\r
+\r
+.macro CHIP_INIT ;r_temp is pushed other Registers should be saved\r
+ ldi r_temp,0\r
+ sts cpsp,r_temp\r
+Init_EEPROM_read:\r
+ push r_bytep\r
+ push r_rwbyte\r
+ sbic _SFR_IO_ADDR(EECR), EEPE\r
+ rjmp Init_EEPROM_read\r
+ ldi r_temp,0\r
+ out _SFR_IO_ADDR(EEARH), r_temp\r
+ ldi r_temp,2\r
+ out _SFR_IO_ADDR(EEARL), r_temp\r
+ sbi _SFR_IO_ADDR(EECR), EERE\r
+ in r_temp,_SFR_IO_ADDR(EEDR)\r
+ sbrs r_temp,7\r
+ rcall hrc_recall_eeprom_func1\r
+ pop r_rwbyte\r
+ pop r_bytep\r
+.endm\r
+\r
+\r
+.macro COMMAND_TABLE\r
+ rjmp h_readscratchpad1\r
+ rjmp h_writescratchpad1\r
+ rjmp h_convert_run1\r
+ rjmp h_readpioregaddr2\r
+ rjmp h_readpioreg2\r
+ rjmp h_readpioregcrc12\r
+ rjmp h_readpioregcrc22\r
+ rjmp h_readchanel2\r
+ rjmp h_readchanel_crc2\r
+ rjmp h_writechanel2\r
+ rjmp h_writecomchanel2\r
+ rjmp h_writesendaa2\r
+ rjmp h_writesendchanel2\r
+ rjmp h_resetactivity2\r
+ rjmp h_writeregaddr2\r
+ rjmp h_writereg2\r
+.endm\r
+\r
+#include "../common/OWRomFunctionsDual.s"\r
+#include "../common/OWTimerInterrupt.s"\r
+\r
+\r
+\r
+; Ab hier Geraeteabhaenging\r
+\r
+#define OW_READ_SCRATCHPAD1 OW_FIRST_COMMAND+0\r
+#define OW_WRITE_SCRATCHPAD1 OW_FIRST_COMMAND+1\r
+#define OW_CONVERT_RUN1 OW_FIRST_COMMAND+2\r
+\r
+#define OW_READ_PIO_REG_ADDR2 OW_FIRST_COMMAND+3\r
+#define OW_READ_PIO_REG2 OW_FIRST_COMMAND+4\r
+#define OW_READ_PIO_REG_CRC12 OW_FIRST_COMMAND+5\r
+#define OW_READ_PIO_REG_CRC22 OW_FIRST_COMMAND+6\r
+#define OW_READ_CHANEL2 OW_FIRST_COMMAND+7\r
+#define OW_READ_CHANEL_CRC2 OW_FIRST_COMMAND+8\r
+#define OW_WRITE_CHANEL2 OW_FIRST_COMMAND+9\r
+#define OW_WRITE_COMCHANEL2 OW_FIRST_COMMAND+10\r
+#define OW_WRITE_SENDAA2 OW_FIRST_COMMAND+11\r
+#define OW_WRITE_SEND_CHANEL2 OW_FIRST_COMMAND+12\r
+#define OW_RESET_ACTIVITY2 OW_FIRST_COMMAND+13\r
+#define OW_WRITE_REG_ADDR2 OW_FIRST_COMMAND+14\r
+#define OW_WRITE_REG2 OW_FIRST_COMMAND+15\r
+\r
+;---------------------------------------------------\r
+; READ COMMAND and start operation\r
+;---------------------------------------------------\r
+\r
+#ifdef _HANDLE_CC_COMMAND_\r
+h_readcommand12:\r
+ clr r_bytep\r
+ cjmp 0x44,hrc_set_convertT12\r
+ ldi r_mode,OW_SLEEP\r
+ rjmp handle_end\r
+#endif\r
+\r
+\r
+h_readcommand1:\r
+ clr r_bytep\r
+#ifndef _DIS_FLASH_\r
+ FLASH_COMMANDS ; muss zu erst sein....\r
+#endif\r
+ cjmp 0xBE,hrc_set_readscratchpad1\r
+ cjmp 0x4E,hrc_set_writescratchpad1\r
+ cjmp 0x44,hrc_set_convertT1\r
+ cjmp 0x48,hrc_copy_scratchpad1\r
+ cjmp 0xB8,hrc_recall_eeprom1\r
+ FW_CONFIG_INFO1\r
+#ifdef _CHANGEABLE_ID_\r
+ CHANGE_ID_COMMANDS\r
+#endif\r
+ ldi r_mode,OW_SLEEP\r
+ rjmp handle_end\r
+\r
+hrc_set_readscratchpad1:\r
+ ldi r_mode,OW_READ_SCRATCHPAD1\r
+ ldi r_sendflag,1\r
+ CRCInit2\r
+ rjmp h_readscratchpad1\r
+\r
+hrc_set_writescratchpad1:\r
+ ldi r_mode,OW_WRITE_SCRATCHPAD1\r
+ ldi r_bytep,2 ;start to write in 2\r
+ rjmp handle_end\r
+\r
+hrc_recall_eeprom1:\r
+ rcall hrc_recall_eeprom_func1\r
+ rjmp handle_end\r
+\r
+#ifdef _HANDLE_CC_COMMAND_\r
+hrc_set_convertT12:\r
+ rjmp hrc_set_convertT1\r
+#endif\r
+\r
+hrc_set_convertT1:\r
+ ldi r_temp,16\r
+ sts gcontrol,r_temp\r
+hrc_set_convertT12b:\r
+ ldi r_mode,OW_CONVERT_RUN1\r
+ ldi r_sendflag,3 ;set bit 0 and 1 for no zero polling\r
+h_convert_run1:\r
+ ldi r_bcount,0\r
+ ldi r_rwbyte,0\r
+ rjmp handle_end_no_bcount \r
+\r
+\r
+\r
+hrc_copy_scratchpad1:\r
+ ldi r_bytep,2\r
+ configZ pack1,r_bytep\r
+ clr r_bytep\r
+hrc_copy_scratchpad_EEPROM_write1:\r
+ sbic _SFR_IO_ADDR(EECR), EEPE \r
+ rjmp hrc_copy_scratchpad_EEPROM_write1\r
+ ldi r_temp, (0<<EEPM1)|(0<<EEPM0)\r
+ out _SFR_IO_ADDR(EECR), r_temp\r
+ ldi r_temp,0\r
+ out _SFR_IO_ADDR(EEARH),r_temp\r
+ out _SFR_IO_ADDR(EEARL), r_bytep\r
+ ld r_rwbyte,Z+\r
+ out _SFR_IO_ADDR(EEDR), r_rwbyte\r
+ sbi _SFR_IO_ADDR(EECR), EEMPE\r
+ sbi _SFR_IO_ADDR(EECR), EEPE\r
+ inc r_bytep\r
+ cpi r_bytep,3\r
+ brne hrc_copy_scratchpad_EEPROM_write1\r
+ rjmp handle_end\r
+\r
+\r
+hrc_recall_eeprom_func1:\r
+ ldi r_bytep,2\r
+ configZ pack1,r_bytep\r
+ clr r_bytep\r
+ clr r_temp\r
+hrc_recall_eeprom_EEPROM_read1:\r
+ sbic _SFR_IO_ADDR(EECR), EEPE\r
+ rjmp hrc_recall_eeprom_EEPROM_read1\r
+ out _SFR_IO_ADDR(EEARH), r_temp\r
+ out _SFR_IO_ADDR(EEARL), r_bytep\r
+ sbi _SFR_IO_ADDR(EECR), EERE\r
+ in r_rwbyte,_SFR_IO_ADDR(EEDR)\r
+ st Z+,r_rwbyte\r
+ inc r_bytep\r
+ cpi r_bytep,3\r
+ brne hrc_recall_eeprom_EEPROM_read1\r
+ ret\r
+\r
+\r
+\r
+\r
+\r
+\r
+;---------------------------------------------------\r
+; READ SCRATCHPAD\r
+;---------------------------------------------------\r
+\r
+h_readscratchpad1:\r
+ cpi r_bytep,8\r
+ breq h_readscratchpad_crc1\r
+ cpi r_bytep,9\r
+ breq h_readscratchpad_all1\r
+ configZ pack1,r_bytep\r
+ ld r_rwbyte,Z\r
+ rjmp h_readscratchpad_endc1\r
+h_readscratchpad_crc1:\r
+ lds r_rwbyte,crc8\r
+h_readscratchpad_endc1:\r
+ inc r_bytep\r
+ ldi r_bcount,1 \r
+ rjmp handle_end\r
+h_readscratchpad_all1:\r
+ rjmp handle_end_sleep\r
+\r
+\r
+\r
+\r
+\r
+;---------------------------------------------------\r
+; WRITE SCRATCHPAD\r
+;---------------------------------------------------\r
+\r
+h_writescratchpad1:\r
+ configZ pack1,r_bytep\r
+ inc r_bytep\r
+ cpi r_bytep,5\r
+ breq h_writescratchpad_all1\r
+ st Z,r_rwbyte\r
+ rjmp handle_end\r
+h_writescratchpad_all1:\r
+ ;ori r_rwbyte,0x1F ; Alle unteren Bits sind immer 1 -->VOC use different\r
+ st Z,r_rwbyte\r
+ rjmp handle_end_sleep\r
+\r
+;*****************************************************************************************************************************************************************************************\r
+;*****************************************************************************************************************************************************************************************\r
+;*****************************************************************************************************************************************************************************************\r
+;*****************************************************************************************************************************************************************************************\r
+;*****************************************************************************************************************************************************************************************\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+h_readcommand2:\r
+ clr r_bytep\r
+#ifndef _DIS_FLASH_\r
+ FLASH_COMMANDS ; muss zu erst sein....\r
+#endif\r
+ cset 0xF0,OW_READ_PIO_REG_ADDR2\r
+ cljmp 0xF5,hrc_readchanel2\r
+ cset 0x5A,OW_WRITE_CHANEL2\r
+ cljmp 0xC3,hrc_reset_activity2\r
+ cset 0xCC,OW_WRITE_REG_ADDR2\r
+ FW_CONFIG_INFO2\r
+#ifdef _CHANGEABLE_ID_\r
+ CHANGE_ID_COMMANDS\r
+#endif\r
+ ldi r_mode,OW_SLEEP\r
+ rjmp handle_end\r
+\r
+\r
+h_readpioregaddr2:\r
+ cpi r_bytep,0 ;erstes Adressbyte ?\r
+ brne h_readpioreg_addr_byte12 ;nein dann weiter\r
+ //andi r_rwbyte,0x1F ; nur Adressen zwischen 0 und 0x1F zulassen\r
+ subi r_rwbyte,0x89 ;beim lesen von 0x88 --> 0xFF inc addr -> 0x00\r
+ sts addr,r_rwbyte ;speichern des ersten bytes\r
+ rjmp handle_end_inc\r
+h_readpioreg_addr_byte12: ;zweiters Addressbyte wird nicht gespeichert!\r
+ ldi r_mode,OW_READ_PIO_REG2 ;weiter zu read Memory\r
+ ;;ldi r_bcount,1 ;ist unten\r
+ ldi r_sendflag,1 ;jetzt sendet der Slave zum Master\r
+ clr r_bytep\r
+h_readpioreg2:\r
+ lds r_bytep,addr\r
+ inc r_bytep\r
+ sts addr,r_bytep\r
+ cpi r_bytep,0x08\r
+ breq h_readpioreg_init_crc2\r
+ brge h_readpioreg_end2 ; groeser dann nix senden\r
+ configZ pack2,r_bytep\r
+ ld r_rwbyte,Z\r
+ ;ldi r_bcount,1\r
+ rjmp handle_end ;sendet das Byte und geht zu h_readmemory\r
+h_readpioreg_init_crc2:; init erstes CRC byte\r
+ lds r_rwbyte,crc16\r
+ com r_rwbyte\r
+ lds r_temp,crc16+1\r
+ com r_temp\r
+ sts crcsave,r_temp\r
+ ldi r_mode,OW_READ_PIO_REG_CRC12\r
+ ;ldi r_bcount,1\r
+ rjmp handle_end\r
+h_readpioreg_end2:\r
+ ldi r_mode,OW_SLEEP\r
+ clr r_sendflag\r
+ rjmp handle_end\r
+h_readpioregcrc12:;init zweites CRC Byte\r
+ lds r_rwbyte,crcsave\r
+ ;ldi r_bcount,1\r
+ ldi r_mode,OW_READ_PIO_REG_CRC22\r
+ rjmp handle_end\r
+h_readpioregcrc22: ; 2. CRC Byte gesendet\r
+ rjmp h_readpioreg_end2\r
+\r
+\r
+hrc_readchanel2:\r
+ ldi r_sendflag,1 ;jetzt sendet der Slave zum Master\r
+ ldi r_mode,OW_READ_CHANEL2\r
+ ldi r_temp,8\r
+ sts gcontrol,r_temp\r
+ rjmp h_readchanel12\r
+h_readchanel2:\r
+ ldi r_temp,4\r
+ sts gcontrol,r_temp\r
+h_readchanel12:\r
+ cpi r_bytep,31\r
+ brge h_readchanelcrc12\r
+ lds r_rwbyte,stat_to_sample\r
+ sts pack2,r_rwbyte //sample \r
+ rjmp handle_end_inc\r
+h_readchanelcrc12:\r
+ lds r_rwbyte,crc16\r
+ com r_rwbyte\r
+ lds r_temp,crc16+1\r
+ com r_temp\r
+ sts crcsave,r_temp\r
+ ldi r_mode,OW_READ_CHANEL_CRC2\r
+ ;ldi r_bcount,1\r
+ rjmp handle_end\r
+h_readchanel_crc2:\r
+ clr r_bytep\r
+ ldi r_mode,OW_READ_CHANEL2\r
+ lds r_rwbyte,crcsave\r
+ rjmp handle_end\r
+ \r
+h_writechanel2:\r
+ sts crcsave,r_rwbyte\r
+ ldi r_mode,OW_WRITE_COMCHANEL2\r
+ rjmp handle_end\r
+h_writecomchanel2:\r
+ com r_rwbyte\r
+ lds r_temp,crcsave\r
+ cp r_rwbyte,r_temp\r
+ breq h_writeok2\r
+ rjmp handle_end_sleep\r
+h_writeok2:\r
+ sts pack2+1,r_rwbyte\r
+ ldi r_temp2,1\r
+ sts gcontrol,r_temp2\r
+ clr r_sendflag\r
+ ldi r_rwbyte,0xAA\r
+ ldi r_mode,OW_WRITE_SENDAA2\r
+ ldi r_sendflag,1 ;jetzt sendet der Slave zum Master\r
+ rjmp handle_end\r
+h_writesendaa2:\r
+ lds r_rwbyte,pack2\r
+ ldi r_mode,OW_WRITE_SEND_CHANEL2\r
+ rjmp handle_end\r
+h_writesendchanel2:\r
+ rjmp handle_end_sleep\r
+\r
+\r
+\r
+hrc_reset_activity2:\r
+ ldi r_temp,2\r
+ sts gcontrol,r_temp\r
+ ldi r_rwbyte,0xAA\r
+ ldi r_mode,OW_RESET_ACTIVITY2\r
+ ldi r_sendflag,1 ;jetzt sendet der Slave zum Master\r
+ rjmp handle_end\r
+h_resetactivity2:\r
+ rjmp handle_end_sleep\r
+\r
+\r
+h_writeregaddr2:\r
+ cpi r_bytep,0 ;erstes Adressbyte ?\r
+ brne h_writeregddr_byte12 ;nein dann weiter\r
+ //andi r_rwbyte,0x1F ; nur Adressen zwischen 0 und 0x1F zulassen\r
+ subi r_rwbyte,0x8B \r
+ brmi h_writereg_end2\r
+ sts addr,r_rwbyte ;speichern des ersten bytes\r
+ rjmp handle_end_inc\r
+h_writeregddr_byte12: ;zweiters Addressbyte wird nicht gespeichert!\r
+ ldi r_mode,OW_WRITE_REG2 ;weiter zu write Memory\r
+ ;;ldi r_bcount,1 ;ist unten\r
+ clr r_bytep\r
+ rjmp handle_end\r
+h_writereg2:\r
+ lds r_temp,addr\r
+ configZ pack2+3,r_temp\r
+ st Z,r_rwbyte\r
+ cpi r_temp,5\r
+ brge h_writereg_end2\r
+ inc r_temp\r
+ sts addr,r_temp\r
+ rjmp handle_end_sleep\r
+ \r
+h_writereg_end2:\r
+ rjmp handle_end_sleep\r
+\r
+\r
+\r
+\r
+\r
+#include "../common/OWPinInterrupt.s"\r
+.end
\ No newline at end of file
tm3d / owSlave2.git / blobdiff