4MHz - Some New double Double Devices
[owSlave2.git] / common / OWDS2401_DS2413.S
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+\r
+// Copyright (c) 2017, Tobias Mueller tm(at)tm3d.de\r
+// All rights reserved. \r
+// \r
+// Redistribution and use in source and binary forms, with or without \r
+// modification, are permitted provided that the following conditions are \r
+// met: \r
+// \r
+//  * Redistributions of source code must retain the above copyright \r
+//    notice, this list of conditions and the following disclaimer. \r
+//  * Redistributions in binary form must reproduce the above copyright \r
+//    notice, this list of conditions and the following disclaimer in the \r
+//    documentation and/or other materials provided with the \r
+//    distribution. \r
+//  * All advertising materials mentioning features or use of this \r
+//    software must display the following acknowledgement: This product \r
+//    includes software developed by tm3d.de and its contributors. \r
+//  * Neither the name of tm3d.de nor the names of its contributors may \r
+//    be used to endorse or promote products derived from this software \r
+//    without specific prior written permission. \r
+// \r
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \r
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT \r
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR \r
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT \r
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, \r
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT \r
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, \r
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY \r
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT \r
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE \r
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. \r
+\r
+#define _CHANGEABLE_ID_\r
+#define _ZERO_POLLING_\r
+//#define _HANDLE_CC_COMMAND_\r
+//#define _DB_\r
+\r
+#include "../common/OWConfig.s"\r
+#include "../common/OWCRC8.s"\r
+\r
+.extern pin_state,1\r
+.extern pin_set,1\r
+.comm resv1,1\r
+\r
+\r
+.macro CHIP_INIT       ;r_temp is pushed other Registers should be saved\r
+.endm\r
+\r
+.macro COMMAND_TABLE\r
+               rjmp h_accessread\r
+               rjmp h_accesswrite\r
+               rjmp h_accesswrite_read\r
+.endm\r
+\r
+#include "../common/OWRomFunctionsDual.s"\r
+#include "../common/OWTimerInterrupt.s"\r
+\r
+\r
+\r
+; Ab hier Geraeteabhaenging\r
+#define OW_ACCESSREAD OW_FIRST_COMMAND+0\r
+#define OW_ACCESSWRITE OW_FIRST_COMMAND+1\r
+#define OW_ACCESSWRITE_READ OW_FIRST_COMMAND+2\r
+\r
+;---------------------------------------------------\r
+;      READ COMMAND and start operation\r
+;---------------------------------------------------\r
+\r
+#ifdef _HANDLE_CC_COMMAND_\r
+/*h_readcommand12:\r
+       clr r_bytep\r
+       cset 0x44,hrc_set_convertT12\r
+       ldi r_mode,OW_SLEEP\r
+       rjmp handle_end*/\r
+#endif\r
+\r
+\r
+h_readcommand1:\r
+       clr r_bytep\r
+#ifndef _DIS_FLASH_\r
+       FLASH_COMMANDS ; muss zu erst sein....\r
+#endif\r
+\r
+/*     cset 0xBE,OW_READ_SCRATCHPAD_ADR1\r
+       cset 0x4E,OW_WRITE_SCRATCHPAD_ADR1\r
+       cjmp 0x44,hrc_set_convertT1\r
+       cjmp 0xB4,hrc_set_convertV1*/\r
+       FW_CONFIG_INFO1\r
+#ifdef _CHANGEABLE_ID_\r
+       CHANGE_ID_COMMANDS\r
+#endif\r
+       rjmp handle_end_sleep\r
+\r
+\r
+\r
+;*****************************************************************************************************************************************************************************************\r
+;*****************************************************************************************************************************************************************************************\r
+;*****************************************************************************************************************************************************************************************\r
+;*****************************************************************************************************************************************************************************************\r
+;*****************************************************************************************************************************************************************************************\r
+\r
+\r
+\r
+\r
+\r
+h_readcommand2:\r
+       clr r_bytep\r
+#ifndef _DIS_FLASH_\r
+       FLASH_COMMANDS ; muss zu erst sein....\r
+#endif\r
+       cjmp 0xF5,hrc_accessread\r
+       cset 0x5A,OW_ACCESSWRITE\r
+/*     cset 0xBE,OW_READ_SCRATCHPAD_ADR2\r
+       cset 0x4E,OW_WRITE_SCRATCHPAD_ADR2\r
+       cjmp 0x44,hrc_set_convertT2\r
+       cjmp 0xB4,hrc_set_convertV2*/\r
+       FW_CONFIG_INFO2\r
+       //cljmp 0x85,hrc_fw_configinfo2\r
+#ifdef _CHANGEABLE_ID_\r
+       CHANGE_ID_COMMANDS\r
+#endif\r
+       rjmp handle_end_sleep\r
+\r
+\r
+hrc_accessread:\r
+       ldi r_sendflag,1\r
+       ldi r_mode,OW_ACCESSREAD\r
+h_accessread:\r
+       lds r_temp,pin_state\r
+       andi r_temp,0x0F\r
+       mov r_rwbyte,r_temp\r
+       com r_rwbyte\r
+       swap r_rwbyte\r
+       andi r_rwbyte,0xF0\r
+       or r_rwbyte,r_temp\r
+       rjmp handle_end\r
+\r
+\r
+\r
+\r
+h_accesswrite_read:\r
+       rjmp handle_end_sleep\r
+       \r
+\r
+\r
+h_accesswrite:\r
+       cpi  r_bytep,1\r
+       breq h_accesswrite_compl\r
+       sts resv1,r_rwbyte\r
+       rjmp handle_end_inc\r
+h_accesswrite_compl:\r
+       com r_rwbyte\r
+       lds r_temp,resv1\r
+       cp r_temp,r_rwbyte\r
+       brne h_accesswrite_error\r
+       sts  pin_set,r_rwbyte\r
+       ldi r_mode,OW_ACCESSWRITE_READ\r
+       ldi r_rwbyte,0xAA\r
+       ldi r_sendflag,1\r
+       rjmp handle_end_inc\r
+h_accesswrite_error:\r
+       rjmp handle_end_sleep\r
+/*\r
+;---------------------------------------------------\r
+;   WRITE SCRATCHPAD\r
+;---------------------------------------------------\r
+h_writescratchpad_adr2:\r
+       lsl r_rwbyte\r
+       lsl r_rwbyte\r
+       lsl r_rwbyte\r
+#if  defined(__AVR_ATtiny25__)\r
+       andi r_rwbyte,0x01 ;nur Page 0 und 1 und das immer wiederholen\r
+#endif\r
+       sts block,r_rwbyte\r
+       ldi r_mode,OW_WRITE_SCRATCHPAD2\r
+       ldi  r_bcount,1 \r
+       rjmp handle_end \r
+h_writescratchpad2:\r
+       cpi  r_bytep,8\r
+       breq h_writescratchpad_all2\r
+       lds  r_temp,block\r
+       add  r_temp,r_bytep\r
+       configZ pack2,r_temp\r
+       st   Z,r_rwbyte\r
+       rjmp handle_end_inc\r
+h_writescratchpad_all2:\r
+       rjmp handle_end_sleep\r
+\r
+\r
+\r
+\r
+\r
+\r
+       */\r
+\r
+\r
+#include "../common/OWPinInterrupt.s"\r
+.end\r