--- /dev/null
+\r
+// Copyright (c) 2017, Tobias Mueller tm(at)tm3d.de\r
+// All rights reserved. \r
+// \r
+// Redistribution and use in source and binary forms, with or without \r
+// modification, are permitted provided that the following conditions are \r
+// met: \r
+// \r
+// * Redistributions of source code must retain the above copyright \r
+// notice, this list of conditions and the following disclaimer. \r
+// * Redistributions in binary form must reproduce the above copyright \r
+// notice, this list of conditions and the following disclaimer in the \r
+// documentation and/or other materials provided with the \r
+// distribution. \r
+// * All advertising materials mentioning features or use of this \r
+// software must display the following acknowledgement: This product \r
+// includes software developed by tm3d.de and its contributors. \r
+// * Neither the name of tm3d.de nor the names of its contributors may \r
+// be used to endorse or promote products derived from this software \r
+// without specific prior written permission. \r
+// \r
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \r
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT \r
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR \r
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT \r
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, \r
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT \r
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, \r
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY \r
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT \r
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE \r
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. \r
+\r
+#define _CHANGEABLE_ID_\r
+#define _ZERO_POLLING_\r
+//#define _HANDLE_CC_COMMAND_\r
+//#define _DB_\r
+\r
+#include "../common/OWConfig.s"\r
+#include "../common/OWCRC16.s"\r
+\r
+.extern pack1,45\r
+.extern counters1,16\r
+\r
+//.extern pack2,45\r
+.extern counters2,16\r
+\r
+#define pack2 pack1 \r
+;same EEPROM for Attiny44 \r
+.extern pin_state,1\r
+.extern pin_set,1\r
+.comm resv1,1\r
+.macro CHIP_INIT ;r_temp is pushed other Registers should be saved\r
+.endm\r
+\r
+.macro COMMAND_TABLE\r
+ rjmp h_writescratchpad1\r
+ rjmp h_writescratchpad_crc1\r
+ rjmp h_readscratchpad1\r
+ rjmp h_copyscratchpad1\r
+ rjmp h_readmemory_addr1\r
+ rjmp h_readmemory1\r
+ rjmp h_readmemorycounter_addr1\r
+ rjmp h_readmemorycounter1\r
+ rjmp h_readmemorycounter_ex1\r
+\r
+ rjmp h_accessread2\r
+ rjmp h_accesswrite2\r
+ rjmp h_accesswrite_read2\r
+.endm\r
+\r
+#include "../common/OWRomFunctionsDual.s"\r
+#include "../common/OWTimerInterrupt.s"\r
+\r
+\r
+\r
+; Ab hier Geraeteabhaenging\r
+#define OW_WRITE_SCRATCHPAD1 OW_FIRST_COMMAND+0\r
+#define OW_WRITE_SCRATCHPAD_CRC1 OW_FIRST_COMMAND+1\r
+#define OW_READ_SCRATCHPAD1 OW_FIRST_COMMAND+2\r
+#define OW_COPY_SCRATCHPAD1 OW_FIRST_COMMAND+3\r
+#define OW_READ_MEMORY_ADDR1 OW_FIRST_COMMAND+4\r
+#define OW_READ_MEMORY1 OW_FIRST_COMMAND+5\r
+#define OW_READ_MEMORYCOUNTER_ADDR1 OW_FIRST_COMMAND+6\r
+#define OW_READ_MEMORYCOUNTER1 OW_FIRST_COMMAND+7\r
+#define OW_READ_MEMORYCOUNTER_EX1 OW_FIRST_COMMAND+8\r
+\r
+#define OW_ACCESSREAD2 OW_FIRST_COMMAND+9\r
+#define OW_ACCESSWRITE2 OW_FIRST_COMMAND+10\r
+#define OW_ACCESSWRITE_READ2 OW_FIRST_COMMAND+11\r
+\r
+\r
+;---------------------------------------------------\r
+; READ COMMAND and start operation\r
+;---------------------------------------------------\r
+\r
+h_readcommand1:\r
+ clr r_bytep\r
+#ifndef _DIS_FLASH_\r
+ FLASH_COMMANDS ; muss zu erst sein....\r
+#endif\r
+ cset 0x0F,OW_WRITE_SCRATCHPAD1\r
+ cjmp 0xAA,hrc_set_readscratchpad1\r
+ cset 0x5A,OW_COPY_SCRATCHPAD1\r
+ cset 0xF0,OW_READ_MEMORY_ADDR1\r
+ cset 0xA5,OW_READ_MEMORYCOUNTER_ADDR1\r
+ FW_CONFIG_INFO1\r
+#ifdef _CHANGEABLE_ID_\r
+ CHANGE_ID_COMMANDS\r
+#endif\r
+ ldi r_mode,OW_SLEEP\r
+ rjmp handle_end\r
+\r
+hrc_set_readscratchpad1:\r
+ ldi r_mode,OW_READ_SCRATCHPAD1\r
+ ldi r_sendflag,1\r
+ rjmp h_readscratchpad1\r
+\r
+h_writescratchpad1:\r
+ configZ pack1,r_bytep\r
+ inc r_bytep\r
+ st Z,r_rwbyte\r
+ cpi r_bytep,2\r
+ breq h_writescratchpad_block1\r
+ brsh h_writescratchpad_set_eoffset1 ;;33\r
+ rjmp handle_end ;handle_end zu weit entfernt fuer br...\r
+h_writescratchpad_set_eoffset1:\r
+ cpi r_bytep,35\r
+ breq h_writescratchpad_setcrc1\r
+ mov r_temp,r_bytep\r
+ subi r_temp,4\r
+ sts pack1+2,r_temp ;AA und PF cleared\r
+ rjmp handle_end\r
+;Start writeing to 32 Byte Block ; skip status byte \r
+h_writescratchpad_block1:\r
+ lds r_temp,pack1 ; Adresse low byte\r
+ andi r_temp,0x1F ;32 byte\r
+ add r_bytep,r_temp ;Zur angegebenen Startadresse springen\r
+ ;ori r_temp,0x20 ; Set PF flag\r
+ sts pack1+2,r_temp ;E4:E0 vorher setzen\r
+ ; Byte 3 ueberspringen\r
+ rjmp handle_end_inc\r
+\r
+h_writescratchpad_setcrc1:\r
+ ;copy crc to pack\r
+ lds r_temp,crc\r
+ com r_temp\r
+ sts pack1+43,r_temp\r
+ lds r_temp,crc+1\r
+ com r_temp ; invertieren , komischer name.....\r
+ sts pack1+44,r_temp\r
+ ldi r_mode,OW_WRITE_SCRATCHPAD_CRC1\r
+ ldi r_sendflag,1\r
+ ldi r_bytep,43\r
+h_writescratchpad_crc1:\r
+ cpi r_bytep,45\r
+ breq h_writescratchpad_crc_end1\r
+ configZ pack1,r_bytep\r
+ ld r_rwbyte,Z\r
+ rjmp handle_end_inc\r
+h_writescratchpad_crc_end1:\r
+ rjmp handle_end_sleep\r
+ \r
+ \r
+h_readscratchpad1:\r
+ cpi r_bytep,35\r
+ breq h_readscratchpad_end1\r
+ cpi r_bytep,3\r
+ brne h_readscratchpad_read_byte1\r
+h_readscratchpad_set_offset1:\r
+ lds r_temp,pack1\r
+ andi r_temp,0x1F\r
+ ldi r_temp2,3\r
+ add r_temp,r_temp2\r
+ mov r_bytep,r_temp\r
+h_readscratchpad_read_byte1:\r
+ configZ pack1,r_bytep\r
+ ld r_rwbyte,Z\r
+ rjmp handle_end_inc\r
+h_readscratchpad_end1:\r
+ rjmp handle_end_sleep\r
+\r
+\r
+\r
+h_copyscratchpad1:\r
+ cpi r_bytep,3\r
+ brsh h_copyscratchpad_ok1\r
+ configZ pack1,r_bytep\r
+ inc r_bytep\r
+ ld r_temp,Z\r
+ cp r_temp,r_rwbyte\r
+ brne h_copyscratchpad_nok1\r
+ cpi r_bytep,3\r
+ breq h_copyscratchpad_ok1\r
+ ldi r_bcount,1 \r
+ rjmp handle_end\r
+h_copyscratchpad_ok1:\r
+ ldi r_rwbyte,0xAA\r
+ ldi r_sendflag,1\r
+ rjmp handle_end\r
+h_copyscratchpad_nok1:\r
+ lds r_temp,pack1+3\r
+ andi r_temp,~0x80\r
+ sts pack1+3,r_temp\r
+ rjmp handle_end_sleep\r
+\r
+\r
+h_readmemory_addr1:\r
+ cpi r_bytep,0\r
+ brne h_readmrmory_addr_byte11\r
+ sts pack1,r_rwbyte\r
+ rjmp handle_end_inc\r
+h_readmrmory_addr_byte11:\r
+ sts pack1+1,r_rwbyte\r
+ ldi r_mode,OW_READ_MEMORY1\r
+ ldi r_sendflag,1\r
+ clr r_bytep\r
+ rjmp h_readmemory21\r
+h_readmemory1:\r
+ lds r_bytep,pack1\r
+ lds r_temp2,pack1+1\r
+ inc r_bytep\r
+ clr r_temp\r
+ adc r_temp2,r_temp\r
+ sbrc r_temp2,1\r
+ rjmp h_readmemory_end1\r
+ sts pack1+1,r_temp\r
+ sts pack1,r_bytep\r
+h_readmemory21:\r
+ lds r_bytep,pack1\r
+ andi r_bytep,0x1F\r
+ configZ pack1+3,r_bytep\r
+ ld r_rwbyte,Z\r
+ rjmp handle_end\r
+h_readmemory_end1:\r
+ rjmp handle_end_sleep\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+h_readmemorycounter_addr1:\r
+ cpi r_bytep,0\r
+ brne h_readmrmorycounter_addr_byte11\r
+ sts pack1,r_rwbyte\r
+ inc r_bytep\r
+ ;ldi r_bcount,1\r
+ rjmp handle_end\r
+h_readmrmorycounter_addr_byte11:\r
+ sts pack1+1,r_rwbyte\r
+ ldi r_mode,OW_READ_MEMORYCOUNTER1\r
+ ;ldi r_bcount,1 \r
+ ldi r_sendflag,1\r
+ clr r_bytep\r
+ rjmp h_readmemorycounter21\r
+h_readmemorycounter1:\r
+ lds r_bytep,pack1\r
+ lds r_temp2,pack1+1\r
+ ldi r_temp,1 ;inc leider kein c flag\r
+ add r_bytep,r_temp\r
+ clr r_temp\r
+ adc r_temp2,r_temp\r
+ mov r_temp,r_bytep\r
+ andi r_temp,0x1F\r
+ breq h_readmemorycounter_next1\r
+ sts pack1+1,r_temp2\r
+ sts pack1,r_bytep\r
+h_readmemorycounter21: ;Lesen von dem worauf die erstenzwei bytes zeigen\r
+ lds r_bytep,pack1\r
+ andi r_bytep,0x1F\r
+ configZ pack1+3,r_bytep\r
+ ld r_rwbyte,Z\r
+ ;ldi r_bcount,1\r
+ rjmp handle_end\r
+//h_readmemorycounter_end:\r
+// ldi r_mode,OW_SLEEP\r
+// clr r_sendflag\r
+// rjmp handle_end\r
+h_readmemorycounter_next1: ; rest lesen\r
+ ldi r_mode,OW_READ_MEMORYCOUNTER_EX1\r
+ ldi r_bytep,34\r
+ lds r_temp2,pack1\r
+ lds r_temp,pack1+1\r
+ lsl r_temp2\r
+ rol r_temp\r
+ cpi r_temp,3\r
+ brne h_readmemorycounter_cFF1\r
+ andi r_temp2,0xC0\r
+ swap r_temp2\r
+\r
+ ;cpi r_temp,0xE0\r
+\r
+ configZ counters1,r_temp2\r
+ ld r_temp,Z+\r
+ sts pack1+35,r_temp \r
+ ld r_temp,Z+\r
+ sts pack1+36,r_temp \r
+ ld r_temp,Z+\r
+ sts pack1+37,r_temp \r
+ ld r_temp,Z+\r
+ sts pack1+38,r_temp \r
+ rjmp h_readmemorycounter_ex1\r
+h_readmemorycounter_cFF1:\r
+ ldi r_temp,0xFF\r
+ sts pack1+35,r_temp \r
+ sts pack1+36,r_temp \r
+ sts pack1+37,r_temp \r
+ sts pack1+38,r_temp \r
+\r
+h_readmemorycounter_ex1:\r
+ inc r_bytep\r
+ cpi r_bytep,45\r
+ breq h_readmemorycounter_ex_end1\r
+ cpi r_bytep,43\r
+ brne h_readmemorycounter_ex21\r
+ lds r_temp,crc\r
+ com r_temp\r
+ sts pack1+43,r_temp\r
+ lds r_temp,crc+1\r
+ com r_temp\r
+ sts pack1+44,r_temp\r
+h_readmemorycounter_ex21:\r
+ ;ldi r_bcount,1\r
+ configZ pack1,r_bytep\r
+ ld r_rwbyte,Z\r
+ rjmp handle_end\r
+h_readmemorycounter_ex_end1:\r
+ lds r_bytep,pack1\r
+ lds r_temp2,pack1+1\r
+ ldi r_temp,1 ;inc leider kein c flag\r
+ add r_bytep,r_temp\r
+ clr r_temp\r
+ adc r_temp2,r_temp\r
+ sbrc r_temp2,1 ;am ene von allem \r
+ rjmp h_readmemorycounter_ex_sleep1\r
+ CRCInit1\r
+ ldi r_mode,OW_READ_MEMORYCOUNTER1\r
+ sts pack1+1,r_temp2\r
+ sts pack1,r_bytep\r
+ rjmp h_readmemorycounter21\r
+h_readmemorycounter_ex_sleep1:\r
+ ldi r_mode,OW_SLEEP\r
+ clr r_sendflag\r
+ rjmp handle_end\r
+\r
+\r
+\r
+\r
+;*****************************************************************************************************************************************************************************************\r
+;*****************************************************************************************************************************************************************************************\r
+;*****************************************************************************************************************************************************************************************\r
+;*****************************************************************************************************************************************************************************************\r
+;*****************************************************************************************************************************************************************************************\r
+\r
+\r
+h_readcommand2:\r
+ clr r_bytep\r
+#ifndef _DIS_FLASH_\r
+ FLASH_COMMANDS ; muss zu erst sein....\r
+#endif\r
+ cjmp 0xF5,hrc_accessread2\r
+ cset 0x5A,OW_ACCESSWRITE2\r
+/* cset 0xBE,OW_READ_SCRATCHPAD_ADR2\r
+ cset 0x4E,OW_WRITE_SCRATCHPAD_ADR2\r
+ cjmp 0x44,hrc_set_convertT2\r
+ cjmp 0xB4,hrc_set_convertV2*/\r
+ FW_CONFIG_INFO2\r
+ //cljmp 0x85,hrc_fw_configinfo2\r
+#ifdef _CHANGEABLE_ID_\r
+ CHANGE_ID_COMMANDS\r
+#endif\r
+ rjmp handle_end_sleep\r
+\r
+\r
+hrc_accessread2:\r
+ ldi r_sendflag,1\r
+ ldi r_mode,OW_ACCESSREAD2\r
+h_accessread2:\r
+ lds r_temp,pin_state\r
+ andi r_temp,0x0F\r
+ mov r_rwbyte,r_temp\r
+ com r_rwbyte\r
+ swap r_rwbyte\r
+ andi r_rwbyte,0xF0\r
+ or r_rwbyte,r_temp\r
+ rjmp handle_end\r
+\r
+\r
+\r
+\r
+h_accesswrite_read2:\r
+ rjmp handle_end_sleep\r
+ \r
+\r
+\r
+h_accesswrite2:\r
+ cpi r_bytep,1\r
+ breq h_accesswrite_compl2\r
+ sts resv1,r_rwbyte\r
+ rjmp handle_end_inc\r
+h_accesswrite_compl2:\r
+ com r_rwbyte\r
+ lds r_temp,resv1\r
+ cp r_temp,r_rwbyte\r
+ brne h_accesswrite_error2\r
+ sts pin_set,r_rwbyte\r
+ ldi r_mode,OW_ACCESSWRITE_READ2\r
+ ldi r_rwbyte,0xAA\r
+ ldi r_sendflag,1\r
+ rjmp handle_end_inc\r
+h_accesswrite_error2:\r
+ rjmp handle_end_sleep\r
+/*\r
+;---------------------------------------------------\r
+; WRITE SCRATCHPAD\r
+;---------------------------------------------------\r
+h_writescratchpad_adr2:\r
+ lsl r_rwbyte\r
+ lsl r_rwbyte\r
+ lsl r_rwbyte\r
+#if defined(__AVR_ATtiny25__)\r
+ andi r_rwbyte,0x01 ;nur Page 0 und 1 und das immer wiederholen\r
+#endif\r
+ sts block,r_rwbyte\r
+ ldi r_mode,OW_WRITE_SCRATCHPAD2\r
+ ldi r_bcount,1 \r
+ rjmp handle_end \r
+h_writescratchpad2:\r
+ cpi r_bytep,8\r
+ breq h_writescratchpad_all2\r
+ lds r_temp,block\r
+ add r_temp,r_bytep\r
+ configZ pack2,r_temp\r
+ st Z,r_rwbyte\r
+ rjmp handle_end_inc\r
+h_writescratchpad_all2:\r
+ rjmp handle_end_sleep\r
+\r
+\r
+\r
+\r
+\r
+\r
+ */\r
+\r
+\r
+#include "../common/OWPinInterrupt.s"\r
+.end\r
tm3d / owSlave2.git / blobdiff