--- /dev/null
+\r
+// Copyright (c) 2017, Tobias Mueller tm(at)tm3d.de\r
+// All rights reserved. \r
+// \r
+// Redistribution and use in source and binary forms, with or without \r
+// modification, are permitted provided that the following conditions are \r
+// met: \r
+// \r
+// * Redistributions of source code must retain the above copyright \r
+// notice, this list of conditions and the following disclaimer. \r
+// * Redistributions in binary form must reproduce the above copyright \r
+// notice, this list of conditions and the following disclaimer in the \r
+// documentation and/or other materials provided with the \r
+// distribution. \r
+// * All advertising materials mentioning features or use of this \r
+// software must display the following acknowledgement: This product \r
+// includes software developed by tm3d.de and its contributors. \r
+// * Neither the name of tm3d.de nor the names of its contributors may \r
+// be used to endorse or promote products derived from this software \r
+// without specific prior written permission. \r
+// \r
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \r
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT \r
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR \r
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT \r
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, \r
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT \r
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, \r
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY \r
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT \r
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE \r
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. \r
+\r
+#define _CHANGEABLE_ID_\r
+#define _ZERO_POLLING_\r
+//#define _HANDLE_CC_COMMAND_\r
+//#define _DB_\r
+\r
+#include "../common/OWConfig.s"\r
+#include "../common/OWCRC8.s"\r
+\r
+\r
+#if defined(__AVR_ATtiny25__)\r
+.extern pack2,16\r
+.extern pack1,16\r
+#else\r
+.extern pack2,64\r
+.extern pack1,64\r
+#endif\r
+.extern DS2438_1_TEMP,2\r
+.extern DS2438_1_VAD,2\r
+.extern DS2438_2_TEMP,2\r
+.extern DS2438_2_VAD,2\r
+.comm block,1 ; Block der augegeben, geschrieben wird (Parameter von READ/WRITE Scratchpad)\r
+\r
+\r
+.macro CHIP_INIT ;r_temp is pushed other Registers should be saved\r
+.endm\r
+\r
+.macro COMMAND_TABLE\r
+ rjmp h_readscratchpad_adr1\r
+ rjmp h_readscratchpad1\r
+ rjmp h_writescratchpad_adr1\r
+ rjmp h_writescratchpad1\r
+ rjmp h_readscratchpad_adr2\r
+ rjmp h_readscratchpad2\r
+ rjmp h_writescratchpad_adr2\r
+ rjmp h_writescratchpad2\r
+.endm\r
+\r
+#include "../common/OWRomFunctionsDual.s"\r
+#include "../common/OWTimerInterrupt.s"\r
+\r
+\r
+\r
+; Ab hier Geraeteabhaenging\r
+#define OW_READ_SCRATCHPAD_ADR1 OW_FIRST_COMMAND+0\r
+#define OW_READ_SCRATCHPAD1 OW_FIRST_COMMAND+1\r
+#define OW_WRITE_SCRATCHPAD_ADR1 OW_FIRST_COMMAND+2\r
+#define OW_WRITE_SCRATCHPAD1 OW_FIRST_COMMAND+3\r
+#define OW_READ_SCRATCHPAD_ADR2 OW_FIRST_COMMAND+4\r
+#define OW_READ_SCRATCHPAD2 OW_FIRST_COMMAND+5\r
+#define OW_WRITE_SCRATCHPAD_ADR2 OW_FIRST_COMMAND+6\r
+#define OW_WRITE_SCRATCHPAD2 OW_FIRST_COMMAND+7\r
+\r
+\r
+;---------------------------------------------------\r
+; READ COMMAND and start operation\r
+;---------------------------------------------------\r
+\r
+#ifdef _HANDLE_CC_COMMAND_\r
+h_readcommand12:\r
+ clr r_bytep\r
+ cset 0x44,hrc_set_convertT12\r
+ ldi r_mode,OW_SLEEP\r
+ rjmp handle_end\r
+#endif\r
+\r
+\r
+h_readcommand1:\r
+ clr r_bytep\r
+#ifndef _DIS_FLASH_\r
+ FLASH_COMMANDS ; muss zu erst sein....\r
+#endif\r
+ cset 0xBE,OW_READ_SCRATCHPAD_ADR1\r
+ cset 0x4E,OW_WRITE_SCRATCHPAD_ADR1\r
+ cjmp 0x44,hrc_set_convertT1\r
+ cjmp 0xB4,hrc_set_convertV1\r
+ FW_CONFIG_INFO1\r
+#ifdef _CHANGEABLE_ID_\r
+ CHANGE_ID_COMMANDS\r
+#endif\r
+ rjmp handle_end_sleep\r
+\r
+\r
+hrc_set_convertT1:\r
+ ldi r_temp,1\r
+ sts gcontrol,r_temp\r
+ lds r_temp,DS2438_1_TEMP\r
+ sts pack1+1,r_temp\r
+ lds r_temp,DS2438_1_TEMP+1\r
+ sts pack1+2,r_temp\r
+ rjmp handle_end_sleep\r
+hrc_set_convertV1:\r
+ lds r_temp,pack1\r
+ sbrs r_temp,3\r
+ rjmp hrc_set_convertVV1\r
+ ldi r_temp,0xF4 //5V\r
+ sts pack1+3,r_temp\r
+ ldi r_temp,0x01\r
+ sts pack1+4,r_temp\r
+ rjmp hrc_set_convertend1\r
+hrc_set_convertVV1:\r
+ ldi r_temp,3\r
+ sts gcontrol,r_temp\r
+ lds r_temp,DS2438_1_VAD\r
+ sts pack1+3,r_temp\r
+ lds r_temp,DS2438_1_VAD+1\r
+ sts pack1+4,r_temp\r
+hrc_set_convertend1:\r
+ rjmp handle_end_sleep\r
+\r
+\r
+\r
+;---------------------------------------------------\r
+; READ SCRATCHPAD\r
+;---------------------------------------------------\r
+\r
+h_readscratchpad_adr1:\r
+ lsl r_rwbyte\r
+ lsl r_rwbyte\r
+ lsl r_rwbyte\r
+#if defined(__AVR_ATtiny25__)\r
+ andi r_rwbyte,0x01 ;nur Page 0 und 1 und das immer wiederholen\r
+#endif\r
+ sts block,r_rwbyte\r
+ ldi r_sendflag,1\r
+ ldi r_mode,OW_READ_SCRATCHPAD1\r
+ CRCInit2\r
+h_readscratchpad1:\r
+ cpi r_bytep,8\r
+ breq h_readscratchpad_crc1\r
+ cpi r_bytep,9\r
+ breq h_readscratchpad_all1\r
+ lds r_temp,block\r
+ add r_temp,r_bytep\r
+ configZ pack1,r_temp\r
+ ld r_rwbyte,Z\r
+ rjmp handle_end_inc\r
+h_readscratchpad_crc1:\r
+ lds r_rwbyte,crc\r
+ rjmp handle_end_inc\r
+h_readscratchpad_all1:\r
+ rjmp handle_end_sleep\r
+\r
+\r
+\r
+\r
+;---------------------------------------------------\r
+; WRITE SCRATCHPAD\r
+;---------------------------------------------------\r
+h_writescratchpad_adr1:\r
+ lsl r_rwbyte\r
+ lsl r_rwbyte\r
+ lsl r_rwbyte\r
+#if defined(__AVR_ATtiny25__)\r
+ andi r_rwbyte,0x01 ;nur Page 0 und 1 und das immer wiederholen\r
+#endif\r
+ sts block,r_rwbyte\r
+ ldi r_mode,OW_WRITE_SCRATCHPAD1\r
+ ldi r_bcount,1 \r
+ rjmp handle_end \r
+h_writescratchpad1:\r
+ cpi r_bytep,8\r
+ breq h_writescratchpad_all1\r
+ lds r_temp,block\r
+ add r_temp,r_bytep\r
+ configZ pack1,r_temp\r
+ st Z,r_rwbyte\r
+ rjmp handle_end_inc\r
+h_writescratchpad_all1:\r
+ rjmp handle_end_sleep\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+#ifdef _HANDLE_CC_COMMAND_\r
+hrc_set_convertT12:\r
+ ldi r_temp,3\r
+ sts gcontrol,r_temp\r
+ lds r_temp,DS2438_2_TEMP\r
+ sts pack2+1,r_temp\r
+ lds r_temp,DS2438_2_TEMP+1\r
+ sts pack2+2,r_temp\r
+ lds r_temp,DS2438_1_TEMP\r
+ sts pack1+1,r_temp\r
+ lds r_temp,DS2438_1_TEMP+1\r
+ sts pack1+2,r_temp\r
+ rjmp handle_end_sleep\r
+#endif\r
+\r
+\r
+;*****************************************************************************************************************************************************************************************\r
+;*****************************************************************************************************************************************************************************************\r
+;*****************************************************************************************************************************************************************************************\r
+;*****************************************************************************************************************************************************************************************\r
+;*****************************************************************************************************************************************************************************************\r
+\r
+\r
+\r
+\r
+\r
+h_readcommand2:\r
+ clr r_bytep\r
+#ifndef _DIS_FLASH_\r
+ FLASH_COMMANDS ; muss zu erst sein....\r
+#endif\r
+ cset 0xBE,OW_READ_SCRATCHPAD_ADR2\r
+ cset 0x4E,OW_WRITE_SCRATCHPAD_ADR2\r
+ cjmp 0x44,hrc_set_convertT2\r
+ cjmp 0xB4,hrc_set_convertV2\r
+ FW_CONFIG_INFO2\r
+ //cljmp 0x85,hrc_fw_configinfo2\r
+#ifdef _CHANGEABLE_ID_\r
+ CHANGE_ID_COMMANDS\r
+#endif\r
+ rjmp handle_end_sleep\r
+\r
+\r
+hrc_set_convertT2:\r
+ ldi r_temp,2\r
+ sts gcontrol,r_temp\r
+ lds r_temp,DS2438_2_TEMP\r
+ sts pack2+1,r_temp\r
+ lds r_temp,DS2438_2_TEMP+1\r
+ sts pack2+2,r_temp\r
+ rjmp handle_end_sleep\r
+hrc_set_convertV2:\r
+ lds r_temp,pack2\r
+ sbrs r_temp,3\r
+ rjmp hrc_set_convertVV2\r
+ ldi r_temp,0xF4\r
+ sts pack2+3,r_temp\r
+ ldi r_temp,0x01\r
+ sts pack2+4,r_temp\r
+ rjmp hrc_set_convertend2\r
+hrc_set_convertVV2:\r
+ ldi r_temp,3\r
+ sts gcontrol,r_temp\r
+ lds r_temp,DS2438_2_VAD\r
+ sts pack2+3,r_temp\r
+ lds r_temp,DS2438_2_VAD+1\r
+ sts pack2+4,r_temp\r
+hrc_set_convertend2:\r
+ rjmp handle_end_sleep\r
+\r
+\r
+\r
+;---------------------------------------------------\r
+; READ SCRATCHPAD\r
+;---------------------------------------------------\r
+\r
+h_readscratchpad_adr2:\r
+ lsl r_rwbyte\r
+ lsl r_rwbyte\r
+ lsl r_rwbyte\r
+#if defined(__AVR_ATtiny25__)\r
+ andi r_rwbyte,0x01 ;nur Page 0 und 1 und das immer wiederholen\r
+#endif\r
+ sts block,r_rwbyte\r
+ ldi r_sendflag,1\r
+ ldi r_mode,OW_READ_SCRATCHPAD2\r
+ CRCInit2\r
+h_readscratchpad2:\r
+ cpi r_bytep,8\r
+ breq h_readscratchpad_crc2\r
+ cpi r_bytep,9\r
+ breq h_readscratchpad_all2\r
+ lds r_temp,block\r
+ add r_temp,r_bytep\r
+ configZ pack2,r_temp\r
+ ld r_rwbyte,Z\r
+ rjmp handle_end_inc\r
+h_readscratchpad_crc2:\r
+ lds r_rwbyte,crc\r
+ rjmp handle_end_inc\r
+h_readscratchpad_all2:\r
+ rjmp handle_end_sleep\r
+\r
+\r
+\r
+\r
+;---------------------------------------------------\r
+; WRITE SCRATCHPAD\r
+;---------------------------------------------------\r
+h_writescratchpad_adr2:\r
+ lsl r_rwbyte\r
+ lsl r_rwbyte\r
+ lsl r_rwbyte\r
+#if defined(__AVR_ATtiny25__)\r
+ andi r_rwbyte,0x01 ;nur Page 0 und 1 und das immer wiederholen\r
+#endif\r
+ sts block,r_rwbyte\r
+ ldi r_mode,OW_WRITE_SCRATCHPAD2\r
+ ldi r_bcount,1 \r
+ rjmp handle_end \r
+h_writescratchpad2:\r
+ cpi r_bytep,8\r
+ breq h_writescratchpad_all2\r
+ lds r_temp,block\r
+ add r_temp,r_bytep\r
+ configZ pack2,r_temp\r
+ st Z,r_rwbyte\r
+ rjmp handle_end_inc\r
+h_writescratchpad_all2:\r
+ rjmp handle_end_sleep\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+#include "../common/OWPinInterrupt.s"\r
+.end\r
tm3d / owSlave2.git / blobdiff