-// Copyright (c) 2015, Tobias Mueller tm(at)tm3d.de
-// All rights reserved.
-//
-// Redistribution and use in source and binary forms, with or without
-// modification, are permitted provided that the following conditions are
-// met:
-//
-// * Redistributions of source code must retain the above copyright
-// notice, this list of conditions and the following disclaimer.
-// * Redistributions in binary form must reproduce the above copyright
-// notice, this list of conditions and the following disclaimer in the
-// documentation and/or other materials provided with the
-// distribution.
-// * All advertising materials mentioning features or use of this
-// software must display the following acknowledgement: This product
-// includes software developed by tm3d.de and its contributors.
-// * Neither the name of tm3d.de nor the names of its contributors may
-// be used to endorse or promote products derived from this software
-// without specific prior written permission.
-//
-// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
-// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-
-
-
-.macro cjmp val,addr
- cpi r_rwbyte,\val
- breq \addr
-.endm
-.macro cljmp val,addr; Weiter sprung, wenn das ziel zu weit entfernt fuer brxx
- cpi r_rwbyte,\val
- brne 1f
- rjmp \addr
-1:
-.endm
-
-.macro cset val,mod ;Nur der Mode wird gesetzt. Abkuerzung da oft nur das noch bleibt
- cpi r_rwbyte,\val
- brne 1f
- ldi r_mode,\mod
- rjmp handle_end
-1:
-.endm
-
-
-
-
-#define OW_SLEEP 0
-#define OW_READ_ROM_COMMAND 1
-#define OW_MATCHROM 2
-#define OW_SEARCHROMS 3 ;next send two bit
-#define OW_SEARCHROMR 4 ; next resive master answer
-#define OW_READ_COMMAND1 5
-#define OW_READ_COMMAND2 6
-#define OW_FWCONFIGINFO1 7
-#define OW_FWCONFIGINFO2 8
-
-.comm idtable,64
-
-#ifdef _CHANGEABLE_ID_
-#define OW_WRITE_NEWID 9
-#define OW_READ_NEWID 10
-#define OW_SET_NEWID 11
-#define OW_FIRST_COMMAND 12
-.comm newid,8
-
-.macro CHANGE_ID_COMMANDS
- cset 0x75,OW_WRITE_NEWID
- cljmp 0xA7,hrc_set_readid
- cljmp 0x79,hrc_set_setid
-.endm
-
-
-#else
-#define OW_FIRST_COMMAND 9
-#endif
-
-#ifndef _DIS_FLASH_
-; test auf run flasher command 0x88 in h_readcommand
-.macro FLASH_COMMANDS
- cpi r_rwbyte,0x88
- brne 1f
- rjmp hrc_jmp_flasher
-1: ldi r_temp,0 ;Anderes Kommando flashmarker zuruecksetzen...
- sts flashmarker,r_temp
-.endm
-#endif
-
-
-.macro FW_CONFIG_INFO1
- cljmp 0x85,hrc_fw_configinfo1
-.endm
-.macro FW_CONFIG_INFO2
- cljmp 0x85,hrc_fw_configinfo2
-.endm
-
-#ifdef _CHANGEABLE_ID_
-; lesen der ID aus dem EEPROM beim Start
-read_EEPROM_ID1:
- ldi r_temp2,lo8(E2END)
- ldi zh,hi8(E2END)
- subi r_temp2,7
- out _SFR_IO_ADDR(EEARH), zh
- ldi r_bytep,0
- ldi zl,lo8(owid1)
- ldi zh,hi8(owid1)
- rjmp read_EEPROM_ID_loop
-read_EEPROM_ID2:
- ldi r_temp2,lo8(E2END)
- ldi zh,hi8(E2END)
- subi r_temp2,15
- out _SFR_IO_ADDR(EEARH), zh
- ldi r_bytep,0
- ldi zl,lo8(owid2)
- ldi zh,hi8(owid2)
-read_EEPROM_ID_loop:
- sbic _SFR_IO_ADDR(EECR), EEPE
- rjmp read_EEPROM_ID_loop
- out _SFR_IO_ADDR(EEARL),r_temp2
- sbi _SFR_IO_ADDR(EECR), EERE
- in r_rwbyte,_SFR_IO_ADDR(EEDR)
- cpi r_rwbyte,0xFF
- breq read_EEPROM_ID_end
- st Z+,r_rwbyte
- inc r_bytep
- inc r_temp2
- cpi r_bytep,8
- brne read_EEPROM_ID_loop
-read_EEPROM_ID_end:
- ret
-#endif
-
-
-
-
-
-
-
-handle_stable:
- rjmp handle_end_no_bcount // sleep eventuell reset, nichts tun und auf Timeout warten
- rjmp h_readromcommand
- rjmp h_matchrom
- rjmp h_searchroms
- rjmp h_searchromr
- rjmp h_readcommand1
- rjmp h_readcommand2
- rjmp h_fwconfiginfo1
- rjmp h_fwconfiginfo2
-#ifdef _CHANGEABLE_ID_
- rjmp h_writeid
- rjmp h_readid
- rjmp h_setid
-#endif
- COMMAND_TABLE
-
-
-
-h_readromcommand:
- clr r_bytep
- cjmp 0x55,hrc_set_matchrom
- cjmp 0xF0,hrc_set_searchrom
- cjmp 0xEC,hrc_set_alarm_search
-
- rjmp handle_end_sleep
-
-#ifndef _DIS_FLASH_
-;sprung zum flasher
-hrc_jmp_flasher:
- lds r_temp,flashmarker
- cpi r_temp,2
- brne hrc_jmp_flasher_inc
- ldi r_temp,0xC0
- push r_temp
- ldi r_temp,0x0E
- push r_temp
- ret ; Direkter Sprung zum Bootloader
-hrc_jmp_flasher_inc:
- inc r_temp
- sts flashmarker,r_temp
- rjmp handle_end_sleep
-#endif
-
-hrc_set_matchrom:
- ldi r_temp,3
- sts srbyte,r_temp ; Beide geraete nehmen an searchrom teil
- ldi r_mode,OW_MATCHROM
- rjmp handle_end
-
-
-
-hrc_set_searchrom:
- ldi r_temp,3
- sts srbyte,r_temp ; Beide geraete nehmen an searchrom teil
- configZ idtable,r_bytep
- rjmp h_searchrom_next_bit
-
-hrc_start_read_command: ;Skip rom und Matchrom ok...
- lds r_temp,srbyte
- cpi r_temp,1
- breq hrc_start_read_command1
- cpi r_temp,2
- breq hrc_start_read_command2
- rjmp handle_end_sleep
- CRCInit1
-hrc_start_read_command1:
- ldi r_mode,OW_READ_COMMAND1
- rjmp handle_end
-hrc_start_read_command2:
- ldi r_mode,OW_READ_COMMAND2
- rjmp handle_end
-
-
-hrc_set_alarm_search:
- lds r_temp,alarmflag
- tst r_temp
- brne hrc_set_searchrom ;alarm flag nicht 0 also gehe zu searchrom
- ; sonst tue nichts
- rjmp handle_end_sleep
-
-hrc_fw_configinfo1:
- ldi r_mode,OW_FWCONFIGINFO1
- ldi r_sendflag,1
- CRCInit2
- rjmp h_fwconfiginfo1
-
-hrc_fw_configinfo2:
- ldi r_mode,OW_FWCONFIGINFO2
- ldi r_sendflag,1
- CRCInit2
- rjmp h_fwconfiginfo2
-
-
-;---------------------------------------------------
-; MATCH ROM
-;---------------------------------------------------
-
-
-h_matchrom:
- lds r_bcount,srbyte
- sbrs r_bcount,0 ;ueberspringe wenn bit 1 =0 also geraet 1 nich mehr im rennen
- rjmp h_matchrom_id2
- configZ owid1,r_bytep
- ld r_temp2,Z
- cp r_temp2,r_rwbyte
- breq h_matchrom_id2
- cbr r_bcount,1 ; loesche geraet
- breq h_matchrom_sleep
-h_matchrom_id2:
- configZ owid2,r_bytep
- ld r_temp2,Z
- cp r_temp2,r_rwbyte
- breq hmr_next_byte
- cbr r_bcount,2 ; loesche geraet
- breq h_matchrom_sleep
-
-hmr_next_byte:
- sts srbyte,r_bcount
- cpi r_bytep,7
- breq hrc_start_read_command ;Starten von Read Command
- rjmp handle_end_inc
-
-h_matchrom_sleep:
- sts srbyte,r_bcount
- rjmp handle_end_sleep
-
-
-;---------------------------------------------------
-; SEARCH ROM
-;---------------------------------------------------
-
-
-h_searchrom_next_bit: ;Setup next Bit of ID
- ld r_temp2,Z
- lds r_temp,srbyte ;srbyte ist ein zeiger auf die bits fuer ein bit im Table
-h_searchrom_next_bit_l2:
- cpi r_temp,3
- breq h_searchrom_next_bit_l1
- lsr r_temp2
- lsr r_temp2
- inc r_temp
- rjmp h_searchrom_next_bit_l2
-h_searchrom_next_bit_l1:
- lsr r_temp2
- rol r_rwbyte ; negiertes bit in rwbyte
- lsr r_temp2
- rol r_rwbyte ; bit in rwbyte
- ldi r_sendflag,1
- ldi r_bcount,0x40 ; zwei bits sensden dann zu Searchromr
- ldi r_mode,OW_SEARCHROMR
- rjmp handle_end_no_bcount
-
-
-
-h_searchroms: ; Modus Send zwei bit
- configZ idtable,r_bytep
- ld r_temp2,Z+
- lds r_temp,srbyte
- cpi r_temp,3
- breq h_searchroms_idd
- cpi r_temp,1
- breq h_searchroms_id1
- cpi r_temp,2
- breq h_searchroms_id2
- rjmp handle_end_sleep ; zur Sicherheit.....
-h_searchroms_idd:
- andi r_rwbyte,0x80
- breq h_searchroms_idd_zero
- ; Master send 1
- sbrc r_temp2,0 ;springe wenn nicht beide bits 0 (id 1 negiert und id 2 negiert)
- rjmp handle_end_sleep ;
- sbrc r_temp2,4 ;id1 set? then skip
- cbr r_temp,1 ; loesche bit 1 in srbyte
- sbrc r_temp2,2 ; springe wenn id 2 gesetzt ist
- cbr r_temp,2 ; loesche bit 2 in srbyte
- sts srbyte,r_temp
- rjmp h_searchroms_idX_end
-h_searchroms_idd_zero:
- sbrc r_temp2,1 ;springe wenn nicht beide 1 (id 1 und id 2 )
- rjmp handle_end_sleep ;beide 1 gehe schlafen
- sbrs r_temp2,4 ;id1 0? then skip
- cbr r_temp,1 ; loesche bit 1 in srbyte
- sbrs r_temp2,2 ; springe wenn id 2 null ist
- cbr r_temp,2 ; loesche bit 2 in srbyte
- sts srbyte,r_temp
- rjmp h_searchroms_idX_end
-h_searchroms_id1:
- andi r_rwbyte,0x80
- breq h_searchroms_id1_zero
- ; Master send 1
- sbrs r_temp2,5 ;id1 set? then skip
- rjmp handle_end_sleep ;
- rjmp h_searchroms_idX_end
-h_searchroms_id1_zero:
- sbrs r_temp2,4 ;id1 set? then skip
- rjmp handle_end_sleep ;
- rjmp h_searchroms_idX_end
-h_searchroms_id2:
- andi r_rwbyte,0x80
- breq h_searchroms_id2_zero
- ; Master send 1
- sbrs r_temp2,3 ;id1 set? then skip
- rjmp handle_end_sleep ;
- rjmp h_searchroms_idX_end
-h_searchroms_id2_zero:
- sbrs r_temp2,2 ;id1 set? then skip
- rjmp handle_end_sleep ;
- rjmp h_searchroms_idX_end
-h_searchroms_idX_end:
- lds r_temp,srbyte
- tst r_temp
- brne h_searchroms_idX_end1
- rjmp handle_end_sleep
-h_searchroms_idX_end1:
- inc r_bytep
- cpi r_bytep,64
- breq h_searchrom_end_ok ;unterschied nur das letzt bit wird wohl nie vorkommen
- rjmp h_searchrom_next_bit
-
-h_searchrom_end_ok:
- clr r_sendflag
- rjmp hrc_start_read_command
-
-h_searchromr: ; stelle um auf empfangen
- clr r_sendflag
- ldi r_mode,OW_SEARCHROMS
- ldi r_bcount,0 ;gehe nach einem bit zu SEARCHROMS
- rjmp handle_end_no_bcount
-
-
-;---------------------------------------------------
-; FW_CONFIG_INFO
-;---------------------------------------------------
-
-h_fwconfiginfo1:
- configZ config_info1,r_bytep
- rjmp h_fwconfiginfo_go
-h_fwconfiginfo2:
- configZ config_info2,r_bytep
-
-h_fwconfiginfo_go:
- cpi r_bytep,16
- breq h_fwconfiginfo_crc
-#ifdef _CRC8_
- cpi r_bytep,17
- breq h_fwconfiginfo_all
-#elif defined _CRC16_
- cpi r_bytep,17
- breq h_fwconfiginfo_crc2
- cpi r_bytep,18
- breq h_fwconfiginfo_all
-#else
- cpi r_bytep,16
- breq h_fwconfiginfo_all
-#warning No CRC known code implemented
-#endif
- ld r_rwbyte,Z
- rjmp handle_end_inc
-h_fwconfiginfo_crc:
- lds r_rwbyte,crc
- rjmp handle_end_inc
-h_fwconfiginfo_crc2:
- lds r_rwbyte,crc+1
- rjmp handle_end_inc
-h_fwconfiginfo_all:
- rjmp handle_end_sleep
-
-
-;---------------------------------------------------
-; CHANGE ROM FUNCTIONS
-;---------------------------------------------------
-
-
-#ifdef _CHANGEABLE_ID_
-
-h_writeid:
- configZ newid,r_bytep
- st Z,r_rwbyte
- cpi r_bytep,7
- breq h_writeid_all
- rjmp handle_end_inc
-h_writeid_all:
- rjmp handle_end_sleep
-
-
-hrc_set_readid:
- ldi r_mode,OW_READ_NEWID
- ldi r_sendflag,1
-h_readid:
- cpi r_bytep,8
- breq h_readid_all
- configZ newid,r_bytep
- ld r_rwbyte,Z
- rjmp handle_end_inc
-h_readid_all:
- clr r_sendflag
- rjmp handle_end_sleep
-
-hrc_set_setid:
- ldi r_mode,OW_SET_NEWID
- ;ldi r_bytep,1 ;start to write in 2
- rjmp handle_end_inc ;set r_bytep to 1!!!
-
-h_setid:
- lds r_bcount,srbyte
- cpi r_bcount,2
- breq h_setid2
-h_setid1:
- configZ owid1,r_bytep
- rjmp h_setido
-h_setid2:
- configZ owid2,r_bytep
-h_setido:
- ld r_temp,Z
- cp r_rwbyte,r_temp
- brne h_setid_bad_code_all
- cpi r_bytep,1
- breq h_setid_set2
- cpi r_bytep,5
- breq h_setid_set3
- cpi r_bytep,6
- breq h_setid_copy_id
- rjmp h_setid_bad_code_all ;sollte eigentlich nicht passieren
-h_setid_set2:
- ldi r_temp,3
- add r_bytep,r_temp
-h_setid_set3:
- inc r_bytep
- rjmp handle_end
-h_setid_copy_id:
- ldi r_temp2,lo8(E2END)
- ldi zh,hi8(E2END)
- ldi r_temp,7
- sbrc r_bcount,1
- ldi r_temp,15
- sub r_temp2,r_temp
- ;ldi r_temp,0 ;kommt nicht vor das ein E2ROM genau n*256+(0 bis 7) byte gross ist
- ;sbc zh
- out _SFR_IO_ADDR(EEARH),zh
- ldi zl,lo8(newid)
- ldi zh,hi8(newid)
- ldi r_bytep,0
-h_setid_EEPROM_write:
- sbic _SFR_IO_ADDR(EECR), EEPE
- rjmp h_setid_EEPROM_write
- ldi r_temp, (0<<EEPM1)|(0<<EEPM0)
- out _SFR_IO_ADDR(EECR), r_temp
- ;nur adresse L schreiben H bleibt aus oben genannten grund gleich.
- out _SFR_IO_ADDR(EEARL),r_temp2
- ld r_rwbyte,Z+
- out _SFR_IO_ADDR(EEDR), r_rwbyte
- sbi _SFR_IO_ADDR(EECR), EEMPE
- sbi _SFR_IO_ADDR(EECR), EEPE
- inc r_bytep
- inc r_temp2
- cpi r_bytep,8
- brne h_setid_EEPROM_write
- //rcall read_EEPROM_ID1
- //rcall read_EEPROM_ID2
- push r_idm1
- push r_idm2
- push xl
- push xh
- rcall init_idtable
- pop xh
- pop xl
- pop r_idm2
- pop r_idm1
-h_setid_bad_code_all:
- rjmp handle_end_sleep
-
-
-
-#endif
-
-
-spause:
- nop
- nop
- nop
- nop
- ret
-
-
-.global OWINIT
-OWINIT:
-
-#ifndef _DIS_FLASH_
-; check for bootloader jumper
- ;vor allen anderen Registerconfigs
- push r_temp
-
- ldi r_temp,(1<<PUD) ;enable pullup
- out _SFR_IO_ADDR(MCUCR) ,r_temp
- sbi _SFR_IO_ADDR(PORTA),PINA5 ;internal pullup on PINA5
- sbi _SFR_IO_ADDR(PORTA),PINA4 ;internal pullup on PINA4
- rcall spause
- sbis _SFR_IO_ADDR(PINA),PINA5
- rjmp owinit_botest_end ;PinA5 nicht auf 1
- sbis _SFR_IO_ADDR(PINA),PINA4
- rjmp owinit_botest_end ;PinA4 nicht auf 1
- cbi _SFR_IO_ADDR(PORTA),PINA4
- sbi _SFR_IO_ADDR(DDRA),PINA4 ;PINA4 AUSGANG und 0
- rcall spause
- sbic _SFR_IO_ADDR(PINA),PINA5
- rjmp owinit_botest_end ;PINA5 nicht 0.... nicht verbunden
- cbi _SFR_IO_ADDR(DDRA),PINA4
- ldi r_temp,0xC0
- push r_temp
- ldi r_temp,0x0E
- push r_temp
- ret ; Direkter Sprung zum Bootloader*/
-owinit_botest_end:
-#endif
- HW_INIT //Microcontroller specific
- CHIP_INIT //1-Wire device specific
- pop r_temp
-init_idtable:
- push yl
- push yh
- push r_temp
- push r_rwbyte
- push r_idn1
- push r_idn2
-#ifdef _CHANGEABLE_ID_
- rcall read_EEPROM_ID1
- rcall read_EEPROM_ID2
-#endif
- ldi r_bytep,8
- ldi r_temp,0
- ldi zl,lo8(idtable)
- ldi zh,hi8(idtable)
- ldi xl,lo8(owid1)
- ldi xh,hi8(owid1)
- ldi yl,lo8(owid2)
- ldi yh,hi8(owid2)
-owinit_odgen1:
- ld r_idm1,X+
- ld r_idm2,Y+
- mov r_idn1,r_idm1
- com r_idn1
- mov r_idn2,r_idm2
- com r_idn2
- ldi r_bcount,8
- mov r_temp,r_idm1
- and r_temp,r_idm2
- mov r_temp2,r_idn1
- and r_temp2,r_idn2
-owinit_odgen2:
- ldi r_mode,0
- lsr r_idm1
- rol r_mode ;6. Bit id1
- lsr r_idn1
- rol r_mode ; 5. Bit id1negiert
- lsr r_idm2
- rol r_mode ;;4. Bit id2
- lsr r_idn2
- rol r_mode ;3. Bit id2 negiert
- lsr r_temp
- rol r_mode ;zweites bit id1 und id2
- lsr r_temp2
- rol r_mode ;erstes bit id1 negiert und id2 negiert
- st Z+,r_mode
- dec r_bcount
- brne owinit_odgen2
- dec r_bytep
- brne owinit_odgen1
- ;copy ids in config bytes
- ldi xl,lo8(owid1)
- ldi xh,hi8(owid1)
- ldi yl,lo8(config_info2+9)
- ldi yh,hi8(config_info2+9)
- ldi r_temp,7
-owinit_cpconfig1:
- ld r_rwbyte,X+
- st Y+,r_rwbyte
- dec r_temp
- brne owinit_cpconfig1
- ldi xl,lo8(owid2)
- ldi xh,hi8(owid2)
- ldi yl,lo8(config_info1+9)
- ldi yh,hi8(config_info1+9)
- ldi r_temp,7
-owinit_cpconfig2:
- ld r_rwbyte,X+
- st Y+,r_rwbyte
- dec r_temp
- brne owinit_cpconfig2
-
-
- ldi r_temp,0
- sts mode,r_temp
- sts bcount,r_temp
- sts alarmflag,r_temp
- RESETZEROMARKER
- pop r_idn2
- pop r_idn1
- pop r_rwbyte
- pop r_temp
- pop yh
- pop yl
-
- ret
-
-.global EXTERN_SLEEP
-EXTERN_SLEEP:
- cli
- push r_temp
- ldi r_temp,0
- sts mode,r_temp ;SLEEP
- sts gcontrol,r_temp
- sts sendflag,r_temp
- sts bcount,r_temp
- RESETZEROMARKER
- pop r_temp
- sei
+// Copyright (c) 2015, Tobias Mueller tm(at)tm3d.de\r
+// All rights reserved. \r
+// \r
+// Redistribution and use in source and binary forms, with or without \r
+// modification, are permitted provided that the following conditions are \r
+// met: \r
+// \r
+// * Redistributions of source code must retain the above copyright \r
+// notice, this list of conditions and the following disclaimer. \r
+// * Redistributions in binary form must reproduce the above copyright \r
+// notice, this list of conditions and the following disclaimer in the \r
+// documentation and/or other materials provided with the \r
+// distribution. \r
+// * All advertising materials mentioning features or use of this \r
+// software must display the following acknowledgement: This product \r
+// includes software developed by tm3d.de and its contributors. \r
+// * Neither the name of tm3d.de nor the names of its contributors may \r
+// be used to endorse or promote products derived from this software \r
+// without specific prior written permission. \r
+// \r
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \r
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT \r
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR \r
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT \r
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, \r
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT \r
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, \r
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY \r
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT \r
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE \r
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. \r
+\r
+\r
+\r
+.macro cjmp val,addr\r
+ cpi r_rwbyte,\val\r
+ breq \addr\r
+.endm\r
+.macro cljmp val,addr; Weiter sprung, wenn das ziel zu weit entfernt fuer brxx\r
+ cpi r_rwbyte,\val\r
+ brne 1f\r
+ rjmp \addr\r
+1:\r
+.endm\r
+\r
+.macro cset val,mod ;Nur der Mode wird gesetzt. Abkuerzung da oft nur das noch bleibt\r
+ cpi r_rwbyte,\val\r
+ brne 1f\r
+ ldi r_mode,\mod\r
+ rjmp handle_end\r
+1:\r
+.endm\r
+\r
+\r
+\r
+\r
+#define OW_SLEEP 0\r
+#define OW_READ_ROM_COMMAND 1\r
+#define OW_MATCHROM 2\r
+#define OW_SEARCHROMS 3 ;next send two bit\r
+#define OW_SEARCHROMR 4 ; next resive master answer\r
+#define OW_READ_COMMAND1 5\r
+#define OW_READ_COMMAND2 6\r
+#define OW_FWCONFIGINFO1 7\r
+#define OW_FWCONFIGINFO2 8\r
+\r
+.comm idtable,64\r
+\r
+#ifdef _CHANGEABLE_ID_\r
+#define OW_WRITE_NEWID 9\r
+#define OW_READ_NEWID 10\r
+#define OW_SET_NEWID 11\r
+#define OW_FIRST_COMMAND 12\r
+.comm newid,8\r
+ \r
+.macro CHANGE_ID_COMMANDS\r
+ cset 0x75,OW_WRITE_NEWID\r
+ cljmp 0xA7,hrc_set_readid\r
+ cljmp 0x79,hrc_set_setid\r
+.endm\r
+\r
+\r
+#else\r
+#define OW_FIRST_COMMAND 9\r
+#endif\r
+\r
+#ifndef _DIS_FLASH_\r
+; test auf run flasher command 0x88 in h_readcommand\r
+.macro FLASH_COMMANDS\r
+ cpi r_rwbyte,0x88\r
+ brne 1f\r
+ rjmp hrc_jmp_flasher\r
+1: ldi r_temp,0 ;Anderes Kommando flashmarker zuruecksetzen...\r
+ sts flashmarker,r_temp\r
+.endm\r
+#endif\r
+\r
+\r
+.macro FW_CONFIG_INFO1\r
+ cljmp 0x85,hrc_fw_configinfo1\r
+.endm\r
+.macro FW_CONFIG_INFO2\r
+ cljmp 0x85,hrc_fw_configinfo2\r
+.endm\r
+\r
+#ifdef _CHANGEABLE_ID_\r
+; lesen der ID aus dem EEPROM beim Start\r
+read_EEPROM_ID1: \r
+ ldi r_temp2,lo8(E2END)\r
+ ldi zh,hi8(E2END)\r
+ subi r_temp2,7\r
+ out _SFR_IO_ADDR(EEARH), zh\r
+ ldi r_bytep,0\r
+ ldi zl,lo8(owid1) \r
+ ldi zh,hi8(owid1)\r
+ rjmp read_EEPROM_ID_loop\r
+read_EEPROM_ID2: \r
+ ldi r_temp2,lo8(E2END)\r
+ ldi zh,hi8(E2END)\r
+ subi r_temp2,15\r
+ out _SFR_IO_ADDR(EEARH), zh\r
+ ldi r_bytep,0\r
+ ldi zl,lo8(owid2) \r
+ ldi zh,hi8(owid2)\r
+read_EEPROM_ID_loop:\r
+ sbic _SFR_IO_ADDR(EECR), EEPE\r
+ rjmp read_EEPROM_ID_loop\r
+ out _SFR_IO_ADDR(EEARL),r_temp2\r
+ sbi _SFR_IO_ADDR(EECR), EERE\r
+ in r_rwbyte,_SFR_IO_ADDR(EEDR)\r
+ cpi r_rwbyte,0xFF\r
+ breq read_EEPROM_ID_end\r
+ st Z+,r_rwbyte\r
+ inc r_bytep\r
+ inc r_temp2\r
+ cpi r_bytep,8\r
+ brne read_EEPROM_ID_loop\r
+read_EEPROM_ID_end:\r
+ ret\r
+#endif\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+handle_stable: \r
+ rjmp handle_end_no_bcount // sleep eventuell reset, nichts tun und auf Timeout warten\r
+ rjmp h_readromcommand \r
+ rjmp h_matchrom \r
+ rjmp h_searchroms \r
+ rjmp h_searchromr\r
+ rjmp h_readcommand1 \r
+ rjmp h_readcommand2\r
+ rjmp h_fwconfiginfo1\r
+ rjmp h_fwconfiginfo2\r
+#ifdef _CHANGEABLE_ID_\r
+ rjmp h_writeid\r
+ rjmp h_readid\r
+ rjmp h_setid\r
+#endif\r
+ COMMAND_TABLE\r
+\r
+\r
+\r
+h_readromcommand:\r
+ clr r_bytep\r
+ cjmp 0x55,hrc_set_matchrom\r
+ cjmp 0xF0,hrc_set_searchrom\r
+ cjmp 0xEC,hrc_set_alarm_search\r
+ \r
+ rjmp handle_end_sleep\r
+\r
+#ifndef _DIS_FLASH_\r
+;sprung zum flasher\r
+hrc_jmp_flasher:\r
+ lds r_temp,flashmarker\r
+ cpi r_temp,2\r
+ brne hrc_jmp_flasher_inc\r
+ ldi r_temp,0xC0\r
+ push r_temp\r
+ ldi r_temp,0x0E\r
+ push r_temp\r
+ ret ; Direkter Sprung zum Bootloader\r
+hrc_jmp_flasher_inc:\r
+ inc r_temp\r
+ sts flashmarker,r_temp\r
+ rjmp handle_end_sleep\r
+#endif\r
+\r
+hrc_set_matchrom:\r
+ ldi r_temp,3\r
+ sts srbyte,r_temp ; Beide geraete nehmen an searchrom teil\r
+ ldi r_mode,OW_MATCHROM\r
+ rjmp handle_end\r
+\r
+\r
+\r
+hrc_set_searchrom: \r
+ ldi r_temp,3\r
+ sts srbyte,r_temp ; Beide geraete nehmen an searchrom teil\r
+ configZ idtable,r_bytep\r
+ rjmp h_searchrom_next_bit\r
+\r
+hrc_start_read_command: ;Skip rom und Matchrom ok...\r
+ lds r_temp,srbyte\r
+ cpi r_temp,1\r
+ breq hrc_start_read_command1\r
+ cpi r_temp,2\r
+ breq hrc_start_read_command2\r
+ rjmp handle_end_sleep\r
+ CRCInit1\r
+hrc_start_read_command1:\r
+ ldi r_mode,OW_READ_COMMAND1\r
+ rjmp handle_end\r
+hrc_start_read_command2:\r
+ ldi r_mode,OW_READ_COMMAND2\r
+ rjmp handle_end\r
+\r
+\r
+hrc_set_alarm_search:\r
+ lds r_temp,alarmflag\r
+ tst r_temp\r
+ brne hrc_set_searchrom ;alarm flag nicht 0 also gehe zu searchrom\r
+ ; sonst tue nichts\r
+ rjmp handle_end_sleep\r
+\r
+hrc_fw_configinfo1:\r
+ ldi r_mode,OW_FWCONFIGINFO1\r
+ ldi r_sendflag,1\r
+ CRCInit2\r
+ rjmp h_fwconfiginfo1\r
+\r
+hrc_fw_configinfo2:\r
+ ldi r_mode,OW_FWCONFIGINFO2\r
+ ldi r_sendflag,1\r
+ CRCInit2\r
+ rjmp h_fwconfiginfo2\r
+\r
+\r
+;---------------------------------------------------\r
+; MATCH ROM\r
+;---------------------------------------------------\r
+ \r
+\r
+h_matchrom:\r
+ lds r_bcount,srbyte\r
+ sbrs r_bcount,0 ;ueberspringe wenn bit 1 =0 also geraet 1 nich mehr im rennen\r
+ rjmp h_matchrom_id2\r
+ configZ owid1,r_bytep\r
+ ld r_temp2,Z\r
+ cp r_temp2,r_rwbyte\r
+ breq h_matchrom_id2\r
+ cbr r_bcount,1 ; loesche geraet\r
+ breq h_matchrom_sleep\r
+h_matchrom_id2:\r
+ configZ owid2,r_bytep\r
+ ld r_temp2,Z\r
+ cp r_temp2,r_rwbyte\r
+ breq hmr_next_byte\r
+ cbr r_bcount,2 ; loesche geraet\r
+ breq h_matchrom_sleep\r
+\r
+hmr_next_byte:\r
+ sts srbyte,r_bcount\r
+ cpi r_bytep,7\r
+ breq hrc_start_read_command ;Starten von Read Command\r
+ rjmp handle_end_inc\r
+\r
+h_matchrom_sleep:\r
+ sts srbyte,r_bcount\r
+ rjmp handle_end_sleep\r
+\r
+\r
+;---------------------------------------------------\r
+; SEARCH ROM\r
+;---------------------------------------------------\r
+\r
+\r
+h_searchrom_next_bit: ;Setup next Bit of ID\r
+ ld r_temp2,Z\r
+ lds r_temp,srbyte ;srbyte ist ein zeiger auf die bits fuer ein bit im Table\r
+h_searchrom_next_bit_l2:\r
+ cpi r_temp,3\r
+ breq h_searchrom_next_bit_l1\r
+ lsr r_temp2\r
+ lsr r_temp2\r
+ inc r_temp\r
+ rjmp h_searchrom_next_bit_l2\r
+h_searchrom_next_bit_l1:\r
+ lsr r_temp2\r
+ rol r_rwbyte ; negiertes bit in rwbyte\r
+ lsr r_temp2\r
+ rol r_rwbyte ; bit in rwbyte\r
+ ldi r_sendflag,1\r
+ ldi r_bcount,0x40 ; zwei bits sensden dann zu Searchromr \r
+ ldi r_mode,OW_SEARCHROMR\r
+ rjmp handle_end_no_bcount\r
+\r
+\r
+\r
+h_searchroms: ; Modus Send zwei bit\r
+ configZ idtable,r_bytep\r
+ ld r_temp2,Z+\r
+ lds r_temp,srbyte\r
+ cpi r_temp,3\r
+ breq h_searchroms_idd\r
+ cpi r_temp,1\r
+ breq h_searchroms_id1\r
+ cpi r_temp,2\r
+ breq h_searchroms_id2\r
+ rjmp handle_end_sleep ; zur Sicherheit.....\r
+h_searchroms_idd:\r
+ andi r_rwbyte,0x80\r
+ breq h_searchroms_idd_zero\r
+ ; Master send 1\r
+ sbrc r_temp2,0 ;springe wenn nicht beide bits 0 (id 1 negiert und id 2 negiert)\r
+ rjmp handle_end_sleep ;\r
+ sbrc r_temp2,4 ;id1 set? then skip\r
+ cbr r_temp,1 ; loesche bit 1 in srbyte\r
+ sbrc r_temp2,2 ; springe wenn id 2 gesetzt ist\r
+ cbr r_temp,2 ; loesche bit 2 in srbyte \r
+ sts srbyte,r_temp\r
+ rjmp h_searchroms_idX_end\r
+h_searchroms_idd_zero:\r
+ sbrc r_temp2,1 ;springe wenn nicht beide 1 (id 1 und id 2 )\r
+ rjmp handle_end_sleep ;beide 1 gehe schlafen\r
+ sbrs r_temp2,4 ;id1 0? then skip\r
+ cbr r_temp,1 ; loesche bit 1 in srbyte\r
+ sbrs r_temp2,2 ; springe wenn id 2 null ist\r
+ cbr r_temp,2 ; loesche bit 2 in srbyte\r
+ sts srbyte,r_temp\r
+ rjmp h_searchroms_idX_end\r
+h_searchroms_id1:\r
+ andi r_rwbyte,0x80\r
+ breq h_searchroms_id1_zero\r
+ ; Master send 1\r
+ sbrs r_temp2,5 ;id1 set? then skip\r
+ rjmp handle_end_sleep ;\r
+ rjmp h_searchroms_idX_end\r
+h_searchroms_id1_zero: \r
+ sbrs r_temp2,4 ;id1 set? then skip\r
+ rjmp handle_end_sleep ;\r
+ rjmp h_searchroms_idX_end\r
+h_searchroms_id2:\r
+ andi r_rwbyte,0x80\r
+ breq h_searchroms_id2_zero\r
+ ; Master send 1\r
+ sbrs r_temp2,3 ;id1 set? then skip\r
+ rjmp handle_end_sleep ;\r
+ rjmp h_searchroms_idX_end\r
+h_searchroms_id2_zero: \r
+ sbrs r_temp2,2 ;id1 set? then skip\r
+ rjmp handle_end_sleep ;\r
+ rjmp h_searchroms_idX_end\r
+h_searchroms_idX_end:\r
+ lds r_temp,srbyte\r
+ tst r_temp\r
+ brne h_searchroms_idX_end1\r
+ rjmp handle_end_sleep\r
+h_searchroms_idX_end1:\r
+ inc r_bytep\r
+ cpi r_bytep,64\r
+ breq h_searchrom_end_ok ;unterschied nur das letzt bit wird wohl nie vorkommen\r
+ rjmp h_searchrom_next_bit\r
+\r
+h_searchrom_end_ok:\r
+ clr r_sendflag\r
+ rjmp hrc_start_read_command\r
+\r
+h_searchromr: ; stelle um auf empfangen\r
+ clr r_sendflag\r
+ ldi r_mode,OW_SEARCHROMS\r
+ ldi r_bcount,0 ;gehe nach einem bit zu SEARCHROMS\r
+ rjmp handle_end_no_bcount\r
+\r
+\r
+;---------------------------------------------------\r
+; FW_CONFIG_INFO\r
+;---------------------------------------------------\r
+\r
+h_fwconfiginfo1:\r
+ configZ config_info1,r_bytep\r
+ rjmp h_fwconfiginfo_go\r
+h_fwconfiginfo2:\r
+ configZ config_info2,r_bytep\r
+\r
+h_fwconfiginfo_go:\r
+ cpi r_bytep,16\r
+ breq h_fwconfiginfo_crc\r
+#ifdef _CRC8_\r
+ cpi r_bytep,17\r
+ breq h_fwconfiginfo_all\r
+#elif defined _CRC16_\r
+ cpi r_bytep,17\r
+ breq h_fwconfiginfo_crc2\r
+ cpi r_bytep,18\r
+ breq h_fwconfiginfo_all\r
+#else\r
+ cpi r_bytep,16\r
+ breq h_fwconfiginfo_all\r
+#warning No CRC known code implemented\r
+#endif\r
+ ld r_rwbyte,Z\r
+ rjmp handle_end_inc\r
+h_fwconfiginfo_crc:\r
+ lds r_rwbyte,crc\r
+ rjmp handle_end_inc\r
+h_fwconfiginfo_crc2:\r
+ lds r_rwbyte,crc+1\r
+ rjmp handle_end_inc\r
+h_fwconfiginfo_all:\r
+ rjmp handle_end_sleep\r
+\r
+\r
+;---------------------------------------------------\r
+; CHANGE ROM FUNCTIONS\r
+;---------------------------------------------------\r
+\r
+\r
+#ifdef _CHANGEABLE_ID_\r
+\r
+h_writeid:\r
+ configZ newid,r_bytep\r
+ st Z,r_rwbyte\r
+ cpi r_bytep,7\r
+ breq h_writeid_all\r
+ rjmp handle_end_inc\r
+h_writeid_all:\r
+ rjmp handle_end_sleep\r
+\r
+\r
+hrc_set_readid:\r
+ ldi r_mode,OW_READ_NEWID\r
+ ldi r_sendflag,1\r
+h_readid:\r
+ cpi r_bytep,8\r
+ breq h_readid_all\r
+ configZ newid,r_bytep\r
+ ld r_rwbyte,Z\r
+ rjmp handle_end_inc\r
+h_readid_all:\r
+ clr r_sendflag\r
+ rjmp handle_end_sleep\r
+\r
+hrc_set_setid:\r
+ ldi r_mode,OW_SET_NEWID\r
+ ;ldi r_bytep,1 ;start to write in 2\r
+ rjmp handle_end_inc ;set r_bytep to 1!!!\r
+\r
+h_setid:\r
+ lds r_bcount,srbyte\r
+ cpi r_bcount,2\r
+ breq h_setid2\r
+h_setid1:\r
+ configZ owid1,r_bytep\r
+ rjmp h_setido\r
+h_setid2:\r
+ configZ owid2,r_bytep\r
+h_setido:\r
+ ld r_temp,Z\r
+ cp r_rwbyte,r_temp\r
+ brne h_setid_bad_code_all\r
+ cpi r_bytep,1\r
+ breq h_setid_set2\r
+ cpi r_bytep,5 \r
+ breq h_setid_set3\r
+ cpi r_bytep,6\r
+ breq h_setid_copy_id\r
+ rjmp h_setid_bad_code_all ;sollte eigentlich nicht passieren\r
+h_setid_set2:\r
+ ldi r_temp,3\r
+ add r_bytep,r_temp\r
+h_setid_set3:\r
+ inc r_bytep\r
+ rjmp handle_end\r
+h_setid_copy_id:\r
+ ldi r_temp2,lo8(E2END)\r
+ ldi zh,hi8(E2END)\r
+ ldi r_temp,7\r
+ sbrc r_bcount,1\r
+ ldi r_temp,15\r
+ sub r_temp2,r_temp\r
+ ;ldi r_temp,0 ;kommt nicht vor das ein E2ROM genau n*256+(0 bis 7) byte gross ist\r
+ ;sbc zh\r
+ out _SFR_IO_ADDR(EEARH),zh\r
+ ldi zl,lo8(newid)\r
+ ldi zh,hi8(newid)\r
+ ldi r_bytep,0\r
+h_setid_EEPROM_write:\r
+ sbic _SFR_IO_ADDR(EECR), EEPE \r
+ rjmp h_setid_EEPROM_write\r
+ ldi r_temp, (0<<EEPM1)|(0<<EEPM0)\r
+ out _SFR_IO_ADDR(EECR), r_temp\r
+ ;nur adresse L schreiben H bleibt aus oben genannten grund gleich.\r
+ out _SFR_IO_ADDR(EEARL),r_temp2\r
+ ld r_rwbyte,Z+\r
+ out _SFR_IO_ADDR(EEDR), r_rwbyte\r
+ sbi _SFR_IO_ADDR(EECR), EEMPE\r
+ sbi _SFR_IO_ADDR(EECR), EEPE\r
+ inc r_bytep\r
+ inc r_temp2\r
+ cpi r_bytep,8\r
+ brne h_setid_EEPROM_write\r
+ //rcall read_EEPROM_ID1\r
+ //rcall read_EEPROM_ID2\r
+ push r_idm1\r
+ push r_idm2\r
+ push xl\r
+ push xh\r
+ rcall init_idtable\r
+ pop xh\r
+ pop xl\r
+ pop r_idm2\r
+ pop r_idm1\r
+h_setid_bad_code_all:\r
+ rjmp handle_end_sleep\r
+\r
+\r
+\r
+#endif\r
+\r
+\r
+spause:\r
+ nop\r
+ nop\r
+ nop\r
+ nop\r
+ ret\r
+\r
+\r
+.global OWINIT\r
+OWINIT:\r
+ \r
+#ifndef _DIS_FLASH_\r
+; check for bootloader jumper\r
+ ;vor allen anderen Registerconfigs\r
+ push r_temp\r
+\r
+ ldi r_temp,(1<<PUD) ;enable pullup \r
+ out _SFR_IO_ADDR(MCUCR) ,r_temp\r
+ sbi _SFR_IO_ADDR(PORTA),PINA5 ;internal pullup on PINA5\r
+ sbi _SFR_IO_ADDR(PORTA),PINA4 ;internal pullup on PINA4\r
+ rcall spause\r
+ sbis _SFR_IO_ADDR(PINA),PINA5\r
+ rjmp owinit_botest_end ;PinA5 nicht auf 1\r
+ sbis _SFR_IO_ADDR(PINA),PINA4\r
+ rjmp owinit_botest_end ;PinA4 nicht auf 1\r
+ cbi _SFR_IO_ADDR(PORTA),PINA4 \r
+ sbi _SFR_IO_ADDR(DDRA),PINA4 ;PINA4 AUSGANG und 0\r
+ rcall spause\r
+ sbic _SFR_IO_ADDR(PINA),PINA5 \r
+ rjmp owinit_botest_end ;PINA5 nicht 0.... nicht verbunden\r
+ cbi _SFR_IO_ADDR(DDRA),PINA4\r
+ ldi r_temp,0xC0\r
+ push r_temp\r
+ ldi r_temp,0x0E\r
+ push r_temp\r
+ ret ; Direkter Sprung zum Bootloader*/\r
+owinit_botest_end:\r
+#endif\r
+ HW_INIT //Microcontroller specific\r
+ CHIP_INIT //1-Wire device specific\r
+ pop r_temp\r
+init_idtable:\r
+ push yl\r
+ push yh\r
+ push r_temp\r
+ push r_rwbyte\r
+ push r_idn1\r
+ push r_idn2\r
+#ifdef _CHANGEABLE_ID_\r
+ rcall read_EEPROM_ID1\r
+ rcall read_EEPROM_ID2\r
+#endif\r
+ ldi r_bytep,8\r
+ ldi r_temp,0\r
+ ldi zl,lo8(idtable)\r
+ ldi zh,hi8(idtable)\r
+ ldi xl,lo8(owid1)\r
+ ldi xh,hi8(owid1)\r
+ ldi yl,lo8(owid2)\r
+ ldi yh,hi8(owid2)\r
+owinit_odgen1:\r
+ ld r_idm1,X+\r
+ ld r_idm2,Y+\r
+ mov r_idn1,r_idm1\r
+ com r_idn1\r
+ mov r_idn2,r_idm2\r
+ com r_idn2\r
+ ldi r_bcount,8\r
+ mov r_temp,r_idm1\r
+ and r_temp,r_idm2\r
+ mov r_temp2,r_idn1\r
+ and r_temp2,r_idn2\r
+owinit_odgen2:\r
+ ldi r_mode,0\r
+ lsr r_idm1\r
+ rol r_mode ;6. Bit id1 \r
+ lsr r_idn1 \r
+ rol r_mode ; 5. Bit id1negiert\r
+ lsr r_idm2\r
+ rol r_mode ;;4. Bit id2 \r
+ lsr r_idn2 \r
+ rol r_mode ;3. Bit id2 negiert\r
+ lsr r_temp \r
+ rol r_mode ;zweites bit id1 und id2\r
+ lsr r_temp2\r
+ rol r_mode ;erstes bit id1 negiert und id2 negiert\r
+ st Z+,r_mode\r
+ dec r_bcount\r
+ brne owinit_odgen2\r
+ dec r_bytep\r
+ brne owinit_odgen1\r
+ ;copy ids in config bytes\r
+ ldi xl,lo8(owid1)\r
+ ldi xh,hi8(owid1)\r
+ ldi yl,lo8(config_info2+9)\r
+ ldi yh,hi8(config_info2+9)\r
+ ldi r_temp,7\r
+owinit_cpconfig1:\r
+ ld r_rwbyte,X+\r
+ st Y+,r_rwbyte\r
+ dec r_temp\r
+ brne owinit_cpconfig1\r
+ ldi xl,lo8(owid2)\r
+ ldi xh,hi8(owid2)\r
+ ldi yl,lo8(config_info1+9)\r
+ ldi yh,hi8(config_info1+9)\r
+ ldi r_temp,7\r
+owinit_cpconfig2:\r
+ ld r_rwbyte,X+\r
+ st Y+,r_rwbyte\r
+ dec r_temp\r
+ brne owinit_cpconfig2\r
+\r
+\r
+ ldi r_temp,0\r
+ sts mode,r_temp\r
+ sts bcount,r_temp\r
+ sts alarmflag,r_temp\r
+ RESETZEROMARKER\r
+ pop r_idn2\r
+ pop r_idn1\r
+ pop r_rwbyte\r
+ pop r_temp\r
+ pop yh\r
+ pop yl\r
+ \r
+ ret\r
+\r
+.global EXTERN_SLEEP\r
+EXTERN_SLEEP:\r
+ cli\r
+ push r_temp\r
+ ldi r_temp,0\r
+ sts mode,r_temp ;SLEEP\r
+ sts gcontrol,r_temp\r
+ sts sendflag,r_temp\r
+ sts bcount,r_temp\r
+ RESETZEROMARKER\r
+ pop r_temp\r
+ sei\r
ret
\ No newline at end of file
tm3d / owSlave2.git / blobdiff