-// Copyright (c) 2015, Tobias Mueller tm(at)tm3d.de
-// All rights reserved.
-//
-// Redistribution and use in source and binary forms, with or without
-// modification, are permitted provided that the following conditions are
-// met:
-//
-// * Redistributions of source code must retain the above copyright
-// notice, this list of conditions and the following disclaimer.
-// * Redistributions in binary form must reproduce the above copyright
-// notice, this list of conditions and the following disclaimer in the
-// documentation and/or other materials provided with the
-// distribution.
-// * All advertising materials mentioning features or use of this
-// software must display the following acknowledgement: This product
-// includes software developed by tm3d.de and its contributors.
-// * Neither the name of tm3d.de nor the names of its contributors may
-// be used to endorse or promote products derived from this software
-// without specific prior written permission.
-//
-// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
-// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-
-
-//#define __4M__
-
-#define OW_PORT _SFR_IO_ADDR(PORTB) //1 Wire Port
-#define OW_PIN _SFR_IO_ADDR(PINB) //1 Wire Pin as number
-#define OW_PINN PORTB2
-#define OW_DDR _SFR_IO_ADDR(DDRB) //pin direction register
-#define TCNT_REG _SFR_IO_ADDR(TCNT0)
-
-#define DB_PORT _SFR_IO_ADDR(PORTB) //1 Wire Port
-#define DB_PIN _SFR_IO_ADDR(PINB) //1 Wire Pin as number
-#define DB_PINN PORTB1
-
-#define SETZEROMARKER sbi _SFR_IO_ADDR(DDRB),5
-#define RESETZEROMARKER cbi _SFR_IO_ADDR(DDRB),5
-#define TESTZEROMARKER sbic _SFR_IO_ADDR(DDRB),5
-
-;#define sdb sbi _SFR_IO_ADDR(PORTB),1
-;#define cdb cbi _SFR_IO_ADDR(PORTB),1
-
-#define TIMER_INTERRUPT TIM0_OVF_vect
-#define PIN_INTERRIPT INT0_vect
-
-#ifdef __4M__
-
-#define OWT_MIN_RESET 70
-#define OWT_RESET2 40
-#define OWT_RESET_PRESENT 15
-#define OWT_PRESENT 50
-#define OWT_WRITE 18
-#define OWT_READ 5
-
-#else
-
-#define OWT_MIN_RESET 140
-#define OWT_RESET2 80
-#define OWT_RESET_PRESENT 30
-#define OWT_PRESENT 130
-#define OWT_WRITE 35
-#define OWT_READ 12
-
-#endif
-
-
-.macro CLEAR_TOV_FLAG
- ldi r_temp,(1<<TOV0)
- out _SFR_IO_ADDR(TIFR),r_temp
-.endm
-
-.macro JMP_NO_TOV
- in r_temp, _SFR_IO_ADDR(TIFR)
- sbrc r_temp,TOV0 ; wenn ueberlauf gleiich weiter
-.endm
-
-.macro CLEAR_INTERRUPT_FLAG
- ldi r_temp,(1<<INTF0);inerrupt flags durch 1 loeschen..... 0 macht nix
- out _SFR_IO_ADDR(GIFR),r_temp
-.endm
-
-.macro EN_TIM_INT
- in r_temp,_SFR_IO_ADDR(TIMSK)
- sbr r_temp,(1<<TOIE0)
- out _SFR_IO_ADDR(TIMSK),r_temp
- ldi r_temp,(1<<TOV0) ;inerrupt flags durch 1 loeschen..... 0 macht nix
- out _SFR_IO_ADDR(TIFR),r_temp
-.endm
-
-.macro DIS_TIM_INT
- in r_temp,_SFR_IO_ADDR(TIMSK)
- cbr r_temp,(1<<TOIE0)
- out _SFR_IO_ADDR(TIMSK),r_temp
-.endm
-
-
-.macro SET_FALLING
- in r_temp,_SFR_IO_ADDR(MCUCR)
- ori r_temp,(1<<ISC01)
- out _SFR_IO_ADDR(MCUCR),r_temp
-.endm
-
-
-.macro SET_FALLING_RESET_SLEEP
- in r_temp,_SFR_IO_ADDR(MCUCR)
- ori r_temp,(1<<ISC01)
- andi r_temp,~(1<<SM1)
- out _SFR_IO_ADDR(MCUCR),r_temp
-.endm
-
-
-.macro HW_INIT
- ;set clock to 8 MHz
- ldi r_temp,0x80;
- out _SFR_IO_ADDR(CLKPR),r_temp
-#ifdef __4M__
- ldi r_temp,(1<<CLKPS0)
-#else
- ldi r_temp,0
-#endif
- out _SFR_IO_ADDR(CLKPR),r_temp
- ;Disable Timer int
- ldi r_temp,0
- out _SFR_IO_ADDR(TIMSK),r_temp ;; is default
- ;Enable Pin int
- ldi r_temp,(1<<INT0)
- out _SFR_IO_ADDR(GIMSK),r_temp
- ;Set Timerclock to Clock / 8 (2us)
- ldi r_temp,(1<<CS01)
- out _SFR_IO_ADDR(TCCR0B),r_temp
- ;OWPin as input
- cbi OW_DDR,OW_PINN ;; is default....
- ;set falling edge
- ldi r_temp,(1<<ISC01)
- out _SFR_IO_ADDR(MCUCR),r_temp
-.endm
+// Copyright (c) 2015, Tobias Mueller tm(at)tm3d.de\r
+// All rights reserved. \r
+// \r
+// Redistribution and use in source and binary forms, with or without \r
+// modification, are permitted provided that the following conditions are \r
+// met: \r
+// \r
+// * Redistributions of source code must retain the above copyright \r
+// notice, this list of conditions and the following disclaimer. \r
+// * Redistributions in binary form must reproduce the above copyright \r
+// notice, this list of conditions and the following disclaimer in the \r
+// documentation and/or other materials provided with the \r
+// distribution. \r
+// * All advertising materials mentioning features or use of this \r
+// software must display the following acknowledgement: This product \r
+// includes software developed by tm3d.de and its contributors. \r
+// * Neither the name of tm3d.de nor the names of its contributors may \r
+// be used to endorse or promote products derived from this software \r
+// without specific prior written permission. \r
+// \r
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \r
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT \r
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR \r
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT \r
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, \r
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT \r
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, \r
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY \r
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT \r
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE \r
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. \r
+\r
+\r
+//#define __4M__\r
+\r
+#define OW_PORT _SFR_IO_ADDR(PORTB) //1 Wire Port\r
+#define OW_PIN _SFR_IO_ADDR(PINB) //1 Wire Pin as number\r
+#define OW_PINN PORTB2\r
+#define OW_DDR _SFR_IO_ADDR(DDRB) //pin direction register\r
+#define TCNT_REG _SFR_IO_ADDR(TCNT0)\r
+\r
+#define DB_PORT _SFR_IO_ADDR(PORTB) //1 Wire Port\r
+#define DB_PIN _SFR_IO_ADDR(PINB) //1 Wire Pin as number\r
+#define DB_PINN PORTB1\r
+\r
+#define SETZEROMARKER sbi _SFR_IO_ADDR(DDRB),5\r
+#define RESETZEROMARKER cbi _SFR_IO_ADDR(DDRB),5\r
+#define TESTZEROMARKER sbic _SFR_IO_ADDR(DDRB),5\r
+\r
+;#define sdb sbi _SFR_IO_ADDR(PORTB),1\r
+;#define cdb cbi _SFR_IO_ADDR(PORTB),1\r
+\r
+#define TIMER_INTERRUPT TIM0_OVF_vect\r
+#define PIN_INTERRIPT INT0_vect\r
+\r
+#ifdef __4M__\r
+\r
+#define OWT_MIN_RESET 70 \r
+#define OWT_RESET2 40\r
+#define OWT_RESET_PRESENT 15\r
+#define OWT_PRESENT 50\r
+#define OWT_WRITE 18\r
+#define OWT_READ 5\r
+\r
+#else\r
+\r
+#define OWT_MIN_RESET 140\r
+#define OWT_RESET2 80\r
+#define OWT_RESET_PRESENT 30\r
+#define OWT_PRESENT 130\r
+#define OWT_WRITE 35\r
+#define OWT_READ 12\r
+\r
+#endif\r
+\r
+\r
+.macro CLEAR_TOV_FLAG\r
+ ldi r_temp,(1<<TOV0)\r
+ out _SFR_IO_ADDR(TIFR),r_temp\r
+.endm\r
+\r
+.macro JMP_NO_TOV\r
+ in r_temp, _SFR_IO_ADDR(TIFR)\r
+ sbrc r_temp,TOV0 ; wenn ueberlauf gleiich weiter\r
+.endm\r
+\r
+.macro CLEAR_INTERRUPT_FLAG \r
+ ldi r_temp,(1<<INTF0);inerrupt flags durch 1 loeschen..... 0 macht nix\r
+ out _SFR_IO_ADDR(GIFR),r_temp\r
+.endm\r
+\r
+.macro EN_TIM_INT\r
+ in r_temp,_SFR_IO_ADDR(TIMSK)\r
+ sbr r_temp,(1<<TOIE0)\r
+ out _SFR_IO_ADDR(TIMSK),r_temp\r
+ ldi r_temp,(1<<TOV0) ;inerrupt flags durch 1 loeschen..... 0 macht nix\r
+ out _SFR_IO_ADDR(TIFR),r_temp\r
+.endm\r
+\r
+.macro DIS_TIM_INT\r
+ in r_temp,_SFR_IO_ADDR(TIMSK)\r
+ cbr r_temp,(1<<TOIE0)\r
+ out _SFR_IO_ADDR(TIMSK),r_temp\r
+.endm\r
+\r
+\r
+.macro SET_FALLING\r
+ in r_temp,_SFR_IO_ADDR(MCUCR)\r
+ ori r_temp,(1<<ISC01)\r
+ out _SFR_IO_ADDR(MCUCR),r_temp\r
+.endm\r
+\r
+\r
+.macro SET_FALLING_RESET_SLEEP\r
+ in r_temp,_SFR_IO_ADDR(MCUCR)\r
+ ori r_temp,(1<<ISC01)\r
+ andi r_temp,~(1<<SM1)\r
+ out _SFR_IO_ADDR(MCUCR),r_temp\r
+.endm\r
+\r
+\r
+.macro HW_INIT\r
+ ;set clock to 8 MHz\r
+ ldi r_temp,0x80;\r
+ out _SFR_IO_ADDR(CLKPR),r_temp\r
+#ifdef __4M__\r
+ ldi r_temp,(1<<CLKPS0)\r
+#else\r
+ ldi r_temp,0\r
+#endif\r
+ out _SFR_IO_ADDR(CLKPR),r_temp\r
+ ;Disable Timer int\r
+ ldi r_temp,0\r
+ out _SFR_IO_ADDR(TIMSK),r_temp ;; is default\r
+ ;Enable Pin int\r
+ ldi r_temp,(1<<INT0)\r
+ out _SFR_IO_ADDR(GIMSK),r_temp\r
+ ;Set Timerclock to Clock / 8 (2us)\r
+ ldi r_temp,(1<<CS01)\r
+ out _SFR_IO_ADDR(TCCR0B),r_temp\r
+ ;OWPin as input\r
+ cbi OW_DDR,OW_PINN ;; is default.... \r
+ ;set falling edge\r
+ ldi r_temp,(1<<ISC01)\r
+ out _SFR_IO_ADDR(MCUCR),r_temp\r
+.endm\r
tm3d / owSlave2.git / blobdiff