1 // Copyright (c) 2017, Tobias Mueller tm(at)tm3d.de
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2 // All rights reserved.
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4 // Redistribution and use in source and binary forms, with or without
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5 // modification, are permitted provided that the following conditions are
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8 // * Redistributions of source code must retain the above copyright
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9 // notice, this list of conditions and the following disclaimer.
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10 // * Redistributions in binary form must reproduce the above copyright
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11 // notice, this list of conditions and the following disclaimer in the
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12 // documentation and/or other materials provided with the
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14 // * All advertising materials mentioning features or use of this
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15 // software must display the following acknowledgment: This product
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16 // includes software developed by tm3d.de and its contributors.
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17 // * Neither the name of tm3d.de nor the names of its contributors may
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18 // be used to endorse or promote products derived from this software
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19 // without specific prior written permission.
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21 // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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22 // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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23 // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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24 // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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25 // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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26 // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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27 // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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28 // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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29 // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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30 // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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31 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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33 //!!!!!Max Program size 7551 Byte
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35 #define F_CPU 8000000UL
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37 #include <avr/interrupt.h>
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38 #include <util/delay.h>
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39 #include <avr/wdt.h>
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40 #include <avr/sleep.h>
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41 #include <avr/pgmspace.h>
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43 extern void OWINIT(void);
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44 extern void EXTERN_SLEEP(void);
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47 //#define FHEM_PLATINE
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51 volatile uint8_t owid1[8]={0x1D, 0x40, 0xDA, 0x84, 0x00, 0x00, 0x05, 0xBD};/**/
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52 volatile uint8_t owid2[8]={0x1D, 0x41, 0xDA, 0x84, 0x00, 0x00, 0x05, 0x8A};/**/
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53 #if RAMEND>260 //defined(__AVR_ATtiny84__) ||defined(__AVR_ATtiny84A__)
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54 uint8_t config_info1[26]={9,13,9,13,9,13,9,13,0x02,19,19,19,19,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00}; //+2 for CRC
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55 uint8_t config_info2[26]={9,13,9,13,9,13,9,13,0x02,19,19,19,19,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00}; //+2 for CRC
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58 #error "Variable not correct"
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61 extern uint8_t mode;
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62 extern uint8_t gcontrol;
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63 extern uint8_t reset_indicator;
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68 volatile uint8_t bytes[45];
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72 uint8_t scratch[32];//3
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73 uint32_t counter; //35
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78 counterpack_t pack1;
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80 //The Memory of both Chips is the same, beause of the small memory of ATTiny44
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83 volatile uint8_t lastcps;
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89 volatile counters_t counters1,counters2;
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92 volatile uint8_t istat;
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93 volatile uint8_t changefromeeprom;
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95 #if defined(__AVR_ATtiny44__) || defined(__AVR_ATtiny84__) ||defined(__AVR_ATtiny44A__) || defined(__AVR_ATtiny84A__)
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96 #define PCINT_VECTOR PCINT0_vect
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97 #define PIN_REG PINA
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98 #define PIN_DDR DDRA
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100 #ifdef FHEM_PLATINE
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101 #define PIN_CH3 (1<<PINA2)
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102 #define PIN_CH2 (1<<PINA1)
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103 #define PIN_CH1 (1<<PINA4)
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104 #define PIN_CH0 (1<<PINA3)
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105 //LEDS
\r#define LPIN_CH2 (1<<PINB0)
\r#define LDD_CH2 DDRB
\r#define LPORT_CH2 PORTB
\r#define LPIN_CH3 (1<<PINA5)
\r#define LDD_CH3 DDRA
\r#define LPORT_CH3 PORTA
\r#define LPIN_CH0 (1<<PINA7)
\r#define LDD_CH0 DDRA
\r#define LPORT_CH0 PORTA
\r#define LPIN_CH1 (1<<PINB1)
\r#define LDD_CH1 DDRB
\r#define LPORT_CH1 PORTB
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107 #define LED2_ON LPORT_CH2|=LPIN_CH2;
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112 #define PIN_CH2 (1<<PINA4)
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113 #define PIN_CH3 (1<<PINA5)
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114 #define PIN_CH0 (1<<PINA6)
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115 #define PIN_CH1 (1<<PINA7)
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119 #define PIN_CH3 (1<<PINA1)
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120 #define PIN_CH2 (1<<PINA0)
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121 #define PIN_CH1 (1<<PINA7)
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122 #define PIN_CH0 (1<<PINA3)
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123 //LEDS
\r#define LPIN_CH0 (1<<PINB1)
\r#define LDD_CH0 DDRB
\r#define LPORT_CH0 PORTB
\r#define LPIN_CH1 (1<<PINB1)
\r#define LDD_CH1 DDRB
\r#define LPORT_CH1 PORTB
\r#define LPIN_CH2 (1<<PINB1)
\r#define LDD_CH2 DDRB
\r#define LPORT_CH2 PORTB
\r#define LPIN_CH3 (1<<PINB1)
\r#define LDD_CH3 DDRB
\r#define LPORT_CH3 PORTB
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124 #define LED2_ON LPORT_CH2&=~LPIN_CH2;
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128 #define TEST_TIMER ((TIMSK0 & (1<<TOIE0))==0)
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134 if (((PIN_REG&PIN_CH2)==0)&&((istat&PIN_CH2)==PIN_CH2)) { counters1.c32[2]++;LED2_ON}
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135 if (((PIN_REG&PIN_CH3)==0)&&((istat&PIN_CH3)==PIN_CH3)) { counters1.c32[3]++; LED2_ON}
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136 if (((PIN_REG&PIN_CH0)==0)&&((istat&PIN_CH0)==PIN_CH0)) { counters2.c32[2]++; LED2_ON}
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137 if (((PIN_REG&PIN_CH1)==0)&&((istat&PIN_CH1)==PIN_CH1)) { counters2.c32[3]++; LED2_ON}
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139 //Reset Switch on the FHEM_BOARD
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140 #ifdef FHEM_PLATINE //clear counter
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141 if ((((PINA&(1<<PINA6)))==0)&&((istat&(1<<PINA6))==(1<<PINA6))) {
\r _delay_ms(100);
\r if (((PINA&(1<<PINA6)))==0) {
\r LPORT_CH3|=LPIN_CH3;
\r _delay_ms(100);
\r counters1.c32[2]=0;
\r counters1.c32[3]=0;
\r counters2.c32[2]=0;
\r counters2.c32[3]=0;
\r //counters1.c32[0]=0;
\r //counters1.c32[1]=0;
\r //counters2.c32[0]=0;
\r //counters2.c32[1]=0;
\r //count Resets
\r counters1.c32[0]++;
\r counters2.c32[0]++;
\r LPORT_CH3&=~LPIN_CH3;
\r }
\r GIFR|=(1<<PCIF0);
\r }
\r #endif
\r istat=PIN_REG;
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142 changefromeeprom=1;
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147 ISR(ANA_COMP_vect) {
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148 if (changefromeeprom==0) return;
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149 if ((ACSR&(1<<ACO))!=0) {
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151 if ((ACSR&(1<<ACO))!=0) {
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153 counters1.c32[1]++;
\r counters2.c32[1]=counters1.c32[1];
\r CLKPR=0x80;//Switch to 4 MHz
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158 for(uint8_t i=0;i<16;i++) {
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160 while(EECR & (1<<EEPE));
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161 EECR = (0<<EEPM1)|(0<<EEPM0);
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163 EEDR = counters1.c8[addr];
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164 EECR |= (1<<EEMPE);
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167 for(uint8_t i=16;i<32;i++) {
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169 while(EECR & (1<<EEPE));
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170 EECR = (0<<EEPM1)|(0<<EEPM0);
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172 EEDR = counters2.c8[addr];
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173 EECR |= (1<<EEMPE);
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176 changefromeeprom=0;
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177 PORTB&=~(1<<PINB1);
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180 #ifdef FHEM_PLATINE
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181 LPORT_CH1|=LPIN_CH1;
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184 LPORT_CH1&=~LPIN_CH1;
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194 #ifdef FHEM_PLATINE
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195 PRR|=(1<<PRUSI); //Switch off usi, dont switch of ADC cause Multiplexer is used for the correct AIN1 pin
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197 PRR|=(1<<PRUSI)|(1<<PRADC); //Switch off usi and adc for save Power
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203 counters1.c32[0]=0;
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204 counters1.c32[2]=0;
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205 counters1.c32[1]=0;
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206 counters1.c32[3]=0;
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207 counters2.c32[0]=0;
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208 counters2.c32[2]=0;
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209 counters2.c32[1]=0;
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210 counters2.c32[3]=0;
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211 changefromeeprom=1;
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213 #if defined(__AVR_ATtiny44__) || defined(__AVR_ATtiny84__) || defined(__AVR_ATtiny24A__)||defined(__AVR_ATtiny44A__) || defined(__AVR_ATtiny84A__)
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215 PORTB|=0xFF-(1<<PINB2); //Make PullUp an all Pins but not OW_PIN
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218 #ifndef _CPULLUP_ // pullup
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219 PORTA&=~(PIN_CH0|PIN_CH1);
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220 PORTA&=~(PIN_CH2|PIN_CH3);
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223 #if defined(FHEM_PLATINE) || defined(W1DAQ) //LEDs
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224 LDD_CH0|=LPIN_CH0;
\r LPORT_CH0&=~LPIN_CH0;
\r LDD_CH1|=LPIN_CH1;
\r LPORT_CH1&=~LPIN_CH1;
\r LDD_CH2|=LPIN_CH2;
\r LPORT_CH2&=~LPIN_CH2;
\r LDD_CH3|=LPIN_CH3;
\r LPORT_CH3&=~LPIN_CH3;
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228 PCMSK0=(PIN_CH0|PIN_CH1|PIN_CH2|PIN_CH3); //Nicht ganz korrekt aber die Bits liegen gleich
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237 for(uint8_t i=0;i<16;i++) {
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239 while(EECR & (1<<EEPE));
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242 counters1.c8[addr]=EEDR;
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244 for(uint8_t i=16;i<32;i++) {
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246 while(EECR & (1<<EEPE));
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249 counters2.c8[addr]=EEDR;
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251 changefromeeprom=0; //Daten neu eingelesen
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252 for (uint8_t i=0;i<4;i++) {
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253 if (counters1.c32[i]==0xFFFFFFFF) {
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254 counters1.c32[i]=0;
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255 changefromeeprom=1; //Daten geaendert
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257 //counters.c32[i]=0;
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259 for (uint8_t i=0;i<4;i++) {
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260 if (counters2.c32[i]==0xFFFFFFFF) {
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261 counters2.c32[i]=0;
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262 changefromeeprom=1; //Daten geaendert
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264 //counters.c32[i]=0;
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267 //ACSR|=(1<<ACD); //Disable Comparator
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268 ADCSRB|=(1<<ACME); //Disable Analog multiplexer
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269 MCUCR &=~(1<<PUD); //All Pins Pullup...
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270 #ifdef FHEM_PLATINE
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272 PORTA&=~(1<<PINA0);//Disable Pullup
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274 DIDR0|=(1<<ADC2D)|(1<<ADC1D); // Disable Digital input on Analog AIN0/AIN1 (PINA1 / PINA2)
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275 PORTA&=~(1<<PINA2); //AIN1
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278 ACSR|=(1<<ACIE)|(1<<ACIS1)|(1<<ACIS0)|(1<<ACBG); //Enabble comperator interrupt Rising edge....(1<<ACIS0) -> minus of Comperator falls down -> output of Comperator rises
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279 #ifdef FHEM_PLATINE
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280 //Switch std AIN1 to A0
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281 ADCSRA&=~(1<<ADEN);
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285 DDRA&=~(1<<PINA6);
\r PCMSK0|=(1<<PCINT6);
\r PORTA|=(1<<PINA6); //Pullup
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288 LPORT_CH0|=LPIN_CH0;
\r _delay_ms(500);
\r LPORT_CH0&=~LPIN_CH0;
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291 LPORT_CH0&=~LPIN_CH0;
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292 _delay_ms(500);
\r LPORT_CH0|=LPIN_CH0;
\r#endif
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295 #ifdef FHEM_PLATINE
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296 if (LPORT_CH2&LPIN_CH2) {
\r _delay_ms(50);
\r LPORT_CH2&=~LPIN_CH2;
\r }
\r
297 if (LPORT_CH1&LPIN_CH1) {
\r _delay_ms(50);
\r LPORT_CH1&=~LPIN_CH1;
\r }
\r
300 if ((LPORT_CH2&LPIN_CH2)==0) {
\r _delay_ms(50);
\r LPORT_CH2|=LPIN_CH2;
\r }
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302 #ifndef FHEM_PLATINE
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303 if ((PINB&(1<<PORTB0))==0) { //Jumper gesetzt ->Ruecksetzen
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304 if ((counters1.c32[2]!=0)||(counters1.c32[3]!=0)||(counters2.c32[2]!=0)||(counters2.c32[3]!=0)) {
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305 counters1.c32[0]++;
\r counters2.c32[0]++;
\r for (uint8_t i=2;i<4;i++) {
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306 counters1.c32[i]=0;
\r
307 counters2.c32[i]=0;
\r
309 //count Resets
\r changefromeeprom=1;
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313 if (((TIMSK0 & (1<<TOIE0))==0)&& (mode==0)) {
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314 MCUCR|=(1<<SE)|(1<<SM1);
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316 MCUCR&=~(1<<ISC01);
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