DS2423_DS2423/DS2423_DS2423.c

   1 // Copyright (c) 2017, Tobias Mueller tm(at)tm3d.de\r
   2 // All rights reserved.\r
   3 //\r
   4 // Redistribution and use in source and binary forms, with or without\r
   5 // modification, are permitted provided that the following conditions are\r
   6 // met:\r
   7 //\r
   8 //  * Redistributions of source code must retain the above copyright\r
   9 //    notice, this list of conditions and the following disclaimer.\r
  10 //  * Redistributions in binary form must reproduce the above copyright\r
  11 //    notice, this list of conditions and the following disclaimer in the\r
  12 //    documentation and/or other materials provided with the\r
  13 //    distribution.\r
  14 //  * All advertising materials mentioning features or use of this\r
  15 //    software must display the following acknowledgment: This product\r
  16 //    includes software developed by tm3d.de and its contributors.\r
  17 //  * Neither the name of tm3d.de nor the names of its contributors may\r
  18 //    be used to endorse or promote products derived from this software\r
  19 //    without specific prior written permission.\r
  20 //\r
  21 // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\r
  22 // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\r
  23 // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\r
  24 // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\r
  25 // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\r
  26 // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
  27 // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\r
  28 // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\r
  29 // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\r
  30 // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
  31 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
  32 \r
  33 //!!!!!Max Program size 7551 Byte\r
  34 #define _CPULLUP_\r
  35 #define F_CPU 8000000UL\r
  36 #include <avr/io.h>\r
  37 #include <avr/interrupt.h>\r
  38 #include <util/delay.h>\r
  39 #include <avr/wdt.h>\r
  40 #include <avr/sleep.h>\r
  41 #include <avr/pgmspace.h>\r
  42 \r
  43 extern void OWINIT(void);\r
  44 extern void EXTERN_SLEEP(void);\r
  45 \r
  46 //#define FHEM_PLATINE\r
  47 \r
  48 volatile uint8_t owid1[8]={0x1D, 0x40, 0xDA, 0x84, 0x00, 0x00, 0x05, 0xBD};/**/\r
  49 volatile uint8_t owid2[8]={0x1D, 0x41, 0xDA, 0x84, 0x00, 0x00, 0x05, 0x8A};/**/\r
  50 #if RAMEND>260 //defined(__AVR_ATtiny84__)   ||defined(__AVR_ATtiny84A__)\r
  51 uint8_t config_info1[26]={9,13,9,13,9,13,9,13,0x02,19,19,19,19,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00}; //+2 for CRC\r
  52 uint8_t config_info2[26]={9,13,9,13,9,13,9,13,0x02,19,19,19,19,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00}; //+2 for CRC\r
  53 #endif\r
  54 #if (owid>128)\r
  55 #error "Variable not correct"\r
  56 #endif\r
  57 \r
  58 extern uint8_t mode;\r
  59 extern uint8_t gcontrol;\r
  60 extern uint8_t reset_indicator;\r
  61 \r
  62 \r
  63 \r
  64 typedef union {\r
  65         volatile uint8_t bytes[45];\r
  66         struct {\r
  67                 uint16_t addr;\r
  68                 uint8_t status;\r
  69                 uint8_t scratch[32];//3\r
  70                 uint32_t counter;  //35\r
  71                 uint32_t zero;   //39\r
  72                 uint16_t crc;  //43\r
  73         };\r
  74 } counterpack_t;\r
  75 counterpack_t pack1;\r
  76 \r
  77 //The Memory of both  Chips is the same, beause of the small memory of ATTiny44\r
  78 #define pack2 pack1\r
  79 \r
  80 volatile uint8_t lastcps;\r
  81 typedef union {\r
  82         uint32_t c32[4];\r
  83         uint8_t c8[16];\r
  84 } counters_t;\r
  85 \r
  86 volatile counters_t counters1,counters2;\r
  87 \r
  88 \r
  89 volatile uint8_t istat;\r
  90 volatile uint8_t changefromeeprom;\r
  91 \r
  92 #if  defined(__AVR_ATtiny44__)  || defined(__AVR_ATtiny84__) ||defined(__AVR_ATtiny44A__)  || defined(__AVR_ATtiny84A__)\r
  93 #define PCINT_VECTOR PCINT0_vect\r
  94 #define PIN_REG PINA\r
  95 #define PIN_DDR DDRA\r
  96 \r
  97 #ifdef FHEM_PLATINE\r
  98 #define PIN_CH3 (1<<PINA2)\r
  99 #define PIN_CH2 (1<<PINA1)\r
 100 #define PIN_CH1 (1<<PINA4)\r
 101 #define PIN_CH0 (1<<PINA3)\r
 102 //LEDS\r#define LPIN_CH2 (1<<PINB0)\r#define LDD_CH2 DDRB\r#define LPORT_CH2 PORTB\r#define LPIN_CH3 (1<<PINA5)\r#define LDD_CH3 DDRA\r#define LPORT_CH3 PORTA\r#define LPIN_CH0 (1<<PINA7)\r#define LDD_CH0 DDRA\r#define LPORT_CH0 PORTA\r#define LPIN_CH1 (1<<PINB1)\r#define LDD_CH1 DDRB\r#define LPORT_CH1 PORTB\r
 103 \r
 104 #define LED2_ON LPORT_CH2|=LPIN_CH2;\r
 105 #else\r
 106 #define LED2_ON\r
 107 #define PIN_CH2 (1<<PINA4)\r
 108 #define PIN_CH3 (1<<PINA5)\r
 109 #define PIN_CH0 (1<<PINA6)\r
 110 #define PIN_CH1 (1<<PINA7)\r
 111 #endif\r
 112 \r
 113 #define TEST_TIMER  ((TIMSK0 & (1<<TOIE0))==0)\r
 114 \r
 115 #endif\r
 116 \r
 117 \r
 118 ISR(PCINT0_vect) {\r
 119         if (((PIN_REG&PIN_CH2)==0)&&((istat&PIN_CH2)==PIN_CH2)) {       counters1.c32[2]++;LED2_ON}\r
 120         if (((PIN_REG&PIN_CH3)==0)&&((istat&PIN_CH3)==PIN_CH3)) {       counters1.c32[3]++;     LED2_ON}\r
 121         if (((PIN_REG&PIN_CH0)==0)&&((istat&PIN_CH0)==PIN_CH0)) {       counters2.c32[2]++;     LED2_ON}\r
 122         if (((PIN_REG&PIN_CH1)==0)&&((istat&PIN_CH1)==PIN_CH1)) {       counters2.c32[3]++;     LED2_ON}\r
 123         \r
 124         //Reset Switch on the FHEM_BOARD\r
 125         #ifdef FHEM_PLATINE  //clear counter\r
 126         if ((((PINA&(1<<PINA6)))==0)&&((istat&(1<<PINA6))==(1<<PINA6)))   {\r            _delay_ms(100);\r                if (((PINA&(1<<PINA6)))==0) {\r                  LPORT_CH3|=LPIN_CH3;\r                   _delay_ms(100);\r                        counters1.c32[2]=0;\r                    counters1.c32[3]=0;\r                    counters2.c32[2]=0;\r                    counters2.c32[3]=0;\r                    //counters1.c32[0]=0;\r                  //counters1.c32[1]=0;\r                  //counters2.c32[0]=0;\r                  //counters2.c32[1]=0;\r                  //count Resets\r                 counters1.c32[0]++;\r                    counters2.c32[0]++;\r                    LPORT_CH3&=~LPIN_CH3;\r          }\r              GIFR|=(1<<PCIF0);\r      }\r      #endif\r istat=PIN_REG;\r
 127         changefromeeprom=1;\r
 128 \r
 129 }\r
 130 \r
 131 \r
 132 ISR(ANA_COMP_vect) {\r
 133         if (changefromeeprom==0) return;\r
 134         if ((ACSR&(1<<ACO))!=0) {\r
 135                 _delay_ms(5);\r
 136                 if ((ACSR&(1<<ACO))!=0) {\r
 137                         //Count Savings\r
 138                         counters1.c32[1]++;\r                    counters2.c32[1]=counters1.c32[1];\r                     CLKPR=0x80;//Switch to 4 MHz\r
 139                         CLKPR=01;\r
 140                         \r
 141                         PORTB|=(1<<PINB1);\r
 142                         EEARH=0;\r
 143                         for(uint8_t i=0;i<16;i++) {\r
 144                                 uint8_t addr=i;\r
 145                                 while(EECR & (1<<EEPE));\r
 146                                 EECR = (0<<EEPM1)|(0<<EEPM0);\r
 147                                 EEARL = i;\r
 148                                 EEDR = counters1.c8[addr];\r
 149                                 EECR |= (1<<EEMPE);\r
 150                                 EECR |= (1<<EEPE);\r
 151                         }\r
 152                         for(uint8_t i=16;i<32;i++) {\r
 153                                 uint8_t addr=i-16;\r
 154                                 while(EECR & (1<<EEPE));\r
 155                                 EECR = (0<<EEPM1)|(0<<EEPM0);\r
 156                                 EEARL = i;\r
 157                                 EEDR = counters2.c8[addr];\r
 158                                 EECR |= (1<<EEMPE);\r
 159                                 EECR |= (1<<EEPE);\r
 160                         }\r
 161                         changefromeeprom=0;\r
 162                         PORTB&=~(1<<PINB1);\r
 163                         CLKPR=0x80;\r
 164                         CLKPR=0;\r
 165 #ifdef FHEM_PLATINE\r
 166                         LPORT_CH1|=LPIN_CH1;\r
 167 #endif\r
 168                         GIFR|=(1<<INTF0);\r
 169                 }\r
 170         }\r
 171         \r
 172 }\r
 173 \r
 174 \r
 175 int main(void){\r
 176         #ifdef FHEM_PLATINE\r
 177         PRR|=(1<<PRUSI);  //Switch off usi, dont switch of ADC cause Multiplexer is used for the correct AIN1 pin\r
 178         #else\r
 179         PRR|=(1<<PRUSI)|(1<<PRADC);  //Switch off usi and adc for save Power\r
 180         #endif\r
 181         OWINIT();\r
 182         \r
 183         pack1.zero=0;\r
 184         pack2.zero=0;\r
 185         counters1.c32[0]=0;\r
 186         counters1.c32[2]=0;\r
 187         counters1.c32[1]=0;\r
 188         counters1.c32[3]=0;\r
 189         counters2.c32[0]=0;\r
 190         counters2.c32[2]=0;\r
 191         counters2.c32[1]=0;\r
 192         counters2.c32[3]=0;\r
 193         changefromeeprom=1;\r
 194         \r
 195         #if  defined(__AVR_ATtiny44__)  || defined(__AVR_ATtiny84__) || defined(__AVR_ATtiny24A__)||defined(__AVR_ATtiny44A__)  || defined(__AVR_ATtiny84A__)\r
 196 \r
 197         PORTB|=0xFF-(1<<PINB2); //Make PullUp an all Pins but not OW_PIN\r
 198         PORTA|=0xFF;\r
 199 \r
 200         #ifndef _CPULLUP_  // pullup\r
 201         PORTA&=~(PIN_CH0|PIN_CH1);\r
 202         PORTA&=~(PIN_CH2|PIN_CH3);\r
 203         #endif\r
 204 \r
 205         #ifdef FHEM_PLATINE  //LEDs\r
 206         LDD_CH0|=LPIN_CH0;\r     LPORT_CH0&=~LPIN_CH0;\r  LDD_CH1|=LPIN_CH1;\r     LPORT_CH1&=~LPIN_CH1;\r  LDD_CH2|=LPIN_CH2;\r     LPORT_CH2&=~LPIN_CH2;\r  LDD_CH3|=LPIN_CH3;\r     LPORT_CH3&=~LPIN_CH3;\r
 207         #endif\r
 208 \r
 209         GIMSK|=(1<<PCIE0);\r
 210         PCMSK0=(PIN_CH0|PIN_CH1|PIN_CH2|PIN_CH3); //Nicht ganz korrekt aber die Bits liegen gleich\r
 211 \r
 212         \r
 213         \r
 214         istat=PINA;\r
 215         #endif\r
 216 \r
 217         EEARH=0;\r
 218         uint8_t addr;\r
 219         for(uint8_t i=0;i<16;i++) {\r
 220                 addr=i;\r
 221                 while(EECR & (1<<EEPE));\r
 222                 EEARL=i;\r
 223                 EECR |= (1<<EERE);\r
 224                 counters1.c8[addr]=EEDR;\r
 225         }\r
 226         for(uint8_t i=16;i<32;i++) {\r
 227                 addr=i-16;\r
 228                 while(EECR & (1<<EEPE));\r
 229                 EEARL=i;\r
 230                 EECR |= (1<<EERE);\r
 231                 counters2.c8[addr]=EEDR;\r
 232         }\r
 233         changefromeeprom=0;  //Daten neu eingelesen\r
 234         for (uint8_t i=0;i<4;i++) {\r
 235                 if (counters1.c32[i]==0xFFFFFFFF) {\r
 236                         counters1.c32[i]=0;\r
 237                         changefromeeprom=1;  //Daten geaendert\r
 238                 }\r
 239                 //counters.c32[i]=0;\r
 240         }\r
 241         for (uint8_t i=0;i<4;i++) {\r
 242                 if (counters2.c32[i]==0xFFFFFFFF) {\r
 243                         counters2.c32[i]=0;\r
 244                         changefromeeprom=1;  //Daten geaendert\r
 245                 }\r
 246                 //counters.c32[i]=0;\r
 247         }\r
 248 \r
 249         //ACSR|=(1<<ACD);  //Disable Comparator\r
 250         ADCSRB|=(1<<ACME); //Disable Analog multiplexer\r
 251         MCUCR &=~(1<<PUD); //All Pins Pullup...\r
 252         #ifdef FHEM_PLATINE\r
 253         DIDR0|=(1<<ADC0D);\r
 254         PORTA&=~(1<<PINA0);//Disable Pullup\r
 255         #else\r
 256         DIDR0|=(1<<ADC2D)|(1<<ADC1D); // Disable Digital input on Analog AIN0/AIN1  (PINA1 / PINA2)\r
 257         PORTA&=~(1<<PINA2); //AIN1\r
 258         #endif\r
 259         ACSR&=~(1<<ACD);\r
 260         ACSR|=(1<<ACIE)|(1<<ACIS1)|(1<<ACIS0)|(1<<ACBG); //Enabble comperator interrupt Rising edge....(1<<ACIS0) -> minus of Comperator falls down -> output of Comperator rises\r
 261         #ifdef FHEM_PLATINE\r
 262         //Switch std AIN1 to A0\r
 263         ADCSRA&=~(1<<ADEN);\r
 264         ADCSRB=(1<<ACME);\r
 265         ADMUX=0;\r
 266         //Taster\r
 267         DDRA&=~(1<<PINA6);\r     PCMSK0|=(1<<PCINT6);\r   PORTA|=(1<<PINA6); //Pullup\r
 268 \r
 269 \r
 270         LPORT_CH0|=LPIN_CH0;\r   _delay_ms(500);\r        LPORT_CH0&=~LPIN_CH0;\r
 271         #endif\r
 272         sei();\r
 273         while(1)   {\r
 274                 #ifdef FHEM_PLATINE\r
 275                 if (LPORT_CH2&LPIN_CH2) {\r                      _delay_ms(50);\r                 LPORT_CH2&=~LPIN_CH2;\r          }\r
 276                 if (LPORT_CH1&LPIN_CH1) {\r                      _delay_ms(50);\r                 LPORT_CH1&=~LPIN_CH1;\r          }\r
 277                 #endif\r
 278                 #ifndef FHEM_PLATINE\r
 279                 if ((PINB&(1<<PORTB0))==0) {  //Jumper gesetzt ->Ruecksetzen\r
 280                         if ((counters1.c32[2]!=0)||(counters1.c32[3]!=0)||(counters2.c32[2]!=0)||(counters2.c32[3]!=0)) {\r
 281                                 counters1.c32[0]++;\r                            counters2.c32[0]++;\r                            for (uint8_t i=2;i<4;i++) {\r
 282                                         counters1.c32[i]=0;\r
 283                                         counters2.c32[i]=0;\r
 284                                 }\r
 285                                 //count Resets\r                         changefromeeprom=1;\r
 286                         }\r
 287                 }\r
 288                 #endif\r
 289                 MCUCR|=(1<<SE);\r
 290                 MCUCR&=~(1<<SM1);\r
 291                 asm("SLEEP");\r
 292         }\r
 293 \r
 294 \r
 295 }\r