DS2450/DS2450.c

   1 \r
   2 // Copyright (c) 2017, Tobias Mueller tm(at)tm3d.de\r
   3 // All rights reserved.\r
   4 //\r
   5 // Redistribution and use in source and binary forms, with or without\r
   6 // modification, are permitted provided that the following conditions are\r
   7 // met:\r
   8 //\r
   9 //  * Redistributions of source code must retain the above copyright\r
  10 //    notice, this list of conditions and the following disclaimer.\r
  11 //  * Redistributions in binary form must reproduce the above copyright\r
  12 //    notice, this list of conditions and the following disclaimer in the\r
  13 //    documentation and/or other materials provided with the\r
  14 //    distribution.\r
  15 //  * All advertising materials mentioning features or use of this\r
  16 //    software must display the following acknowledgement: This product\r
  17 //    includes software developed by tm3d.de and its contributors.\r
  18 //  * Neither the name of tm3d.de nor the names of its contributors may\r
  19 //    be used to endorse or promote products derived from this software\r
  20 //    without specific prior written permission.\r
  21 //\r
  22 // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\r
  23 // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\r
  24 // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\r
  25 // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\r
  26 // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\r
  27 // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
  28 // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\r
  29 // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\r
  30 // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\r
  31 // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
  32 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
  33 \r
  34 #define F_CPU 8000000UL\r
  35 #include <avr/io.h>\r
  36 #include <avr/interrupt.h>\r
  37 #include <util/delay.h>\r
  38 #include <avr/wdt.h>\r
  39 #include <avr/sleep.h>\r
  40 #include <avr/pgmspace.h>\r
  41 #include "../common/I2C/TWI_Master.h"\r
  42 \r
  43 extern void OWINIT();\r
  44 extern void EXTERN_SLEEP();\r
  45 \r
  46 uint8_t owid[8]={0x20, 0xA2, 0xD9, 0x84, 0x00, 0x16, 0x02, 0x5D};/**/\r
  47 uint8_t config_info[26]={0x06,0x09,0x06,0x09,0x06,0x09,0x06,0x09,0x02,20,20,20,20,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00};\r
  48 \r
  49 #if (owid>128) \r
  50 #error "Variable not correct"\r
  51 #endif\r
  52 \r
  53 extern volatile uint8_t mode;\r
  54 extern uint8_t gcontrol;\r
  55 extern uint8_t reset_indicator;\r
  56 extern uint8_t alarmflag;\r
  57 \r
  58 \r
  59 \r
  60 #if  defined(__AVR_ATtiny24__)||defined(__AVR_ATtiny44__)  || defined(__AVR_ATtiny84__) || defined(__AVR_ATtiny24A__)||defined(__AVR_ATtiny44A__)  || defined(__AVR_ATtiny84A__)\r
  61 ISR(WATCHDOG_vect) {\r
  62         #else\r
  63         ISR(WDT_vect) {\r
  64         // mode=0;\r
  65                 #endif\r
  66         //wdcounter++;\r
  67                         if (reset_indicator==1) reset_indicator++;\r
  68                 else if (reset_indicator==2) mode=0;\r
  69         }\r
  70 \r
  71 \r
  72 typedef union {\r
  73         volatile uint8_t bytes[0x20];\r
  74         struct {\r
  75                 //Page0\r
  76                 uint16_t A;  //0\r
  77                 uint16_t B;  //2\r
  78                 uint16_t C;  //4\r
  79                 uint16_t D;  //6\r
  80                 //Page1\r
  81                 uint8_t CSA1;\r
  82                 uint8_t CSA2;\r
  83                 uint8_t CSB1;\r
  84                 uint8_t CSB2;\r
  85                 uint8_t CSC1;\r
  86                 uint8_t CSC2;\r
  87                 uint8_t CSD1;\r
  88                 uint8_t CSD2;\r
  89                 //Page2\r
  90                 uint8_t LA;\r
  91                 uint8_t HA;\r
  92                 uint8_t LB;\r
  93                 uint8_t HB;\r
  94                 uint8_t LC;\r
  95                 uint8_t HC;\r
  96                 uint8_t LD;\r
  97                 uint8_t HD;\r
  98                 //Page3\r
  99                 uint8_t FC1;\r
 100                 uint8_t FC2;\r
 101                 uint8_t FC3;\r
 102                 uint8_t FC4;\r
 103                 uint8_t VCCP;\r
 104                 uint8_t FC5;\r
 105                 uint8_t FC6;\r
 106                 uint8_t FC7;\r
 107                 uint8_t convc1;\r
 108                 uint8_t convc2;\r
 109                 \r
 110                 \r
 111         };\r
 112 } pack_t;\r
 113 volatile pack_t pack;\r
 114 \r
 115 \r
 116 #if  defined(__AVR_ATtiny24__)||defined(__AVR_ATtiny44__)  || defined(__AVR_ATtiny84__)||defined(__AVR_ATtiny24A__)||defined(__AVR_ATtiny44A__)  || defined(__AVR_ATtiny84A__)\r
 117 #define AD_PORT PORTA\r
 118 #define AD_DDR DDRA\r
 119 #endif\r
 120 \r
 121 #if  defined(__AVR_ATmega168__)||defined(__AVR_ATmega168A__) ||defined(__AVR_ATmega328__) ||defined(__AVR_ATmega328P__) ||defined(__AVR_ATmega328PB__) \r
 122 #define AD_PORT PORTC\r
 123 #define AD_DDR DDRC\r
 124 #endif\r
 125 \r
 126 \r
 127 int main(void){\r
 128         pack.A=0;\r
 129         pack.B=0;\r
 130         pack.C=0;\r
 131         pack.D=0;\r
 132         pack.CSA1=0x08;\r
 133         pack.CSA2=0x8C;\r
 134         pack.CSB1=0x08;\r
 135         pack.CSB2=0x8C;\r
 136         pack.CSC1=0x08;\r
 137         pack.CSC2=0x8C;\r
 138         pack.CSD1=0x08;\r
 139         pack.CSD2=0x8C;\r
 140         pack.HA=0xFF;\r
 141         pack.LA=0x00;\r
 142         pack.HB=0xFF;\r
 143         pack.LB=0x00;\r
 144         pack.HC=0xFF;\r
 145         pack.LC=0x00;\r
 146         pack.HD=0xFF;\r
 147         pack.LD=0x00;\r
 148         pack.VCCP=0;\r
 149          MCUCR &=~(1<<PUD); //All Pins Pullup...\r
 150          MCUCR |=(1<<BODS);\r
 151          MCUSR=0;\r
 152 \r
 153 \r
 154 \r
 155         OWINIT();\r
 156         DDRC=0xFF;\r
 157         DDRB=0xFF;\r
 158         DDRD=0xFF-(1<<PIND2);\r
 159         PORTB=0xFF;\r
 160         PORTC=0xFF;\r
 161         PORTD=0xFF-(1<<PIND2);\r
 162         PRR=0xCF;\r
 163                 \r
 164         MCUCR &=~(1<<PUD); //All Pins Pullup...\r
 165         //MCUCR |=(1<<BODS);\r
 166         //PORTA&=~((1<<PINA0)|(1<<PINA1)|(1<<PINA2)|(1<<PINA3));\r
 167 \r
 168         //ADCSRA=(1<<ADEN)|(1<ADPS0)|(1<<ADPS2);\r
 169 \r
 170         \r
 171                 WDTCSR |= (1<<WDCE) |(1<<WDE);   // Enable the WD Change Bit//| (1<<WDE)\r
 172                 WDTCSR  =   (1<<WDIE) |              // Enable WDT Interrupt\r
 173                 (1<<WDP2) | (1<<WDP0);   // Set Timeout to ~8 seconds\r
 174         gcontrol=1;\r
 175         ADCSRB|=(1<<ADLAR); \r
 176         sei();\r
 177         \r
 178         //DDRB|=(1<<PINB1);\r
 179 \r
 180     while(1)   {\r
 181 \r
 182 \r
 183                 if (gcontrol) {\r
 184                         //PORTB|=(1<<PINB1);\r
 185                         uint8_t bb=1;\r
 186                         uint8_t bb1=1;\r
 187                         for(uint8_t i=0;i<4;i++){\r
 188                                 if (pack.convc1&bb1) {\r
 189                                         if (pack.convc2&(bb)) {pack.bytes[i*2]=0;pack.bytes[i*2+1]=0;}\r
 190                                         bb=bb<<1;\r
 191                                         if (pack.convc2&(bb)) {pack.bytes[i*2]=0xFF;pack.bytes[i*2+1]=0xFF;}\r
 192                                         bb=bb<<1;\r
 193                                 } else bb=bb<<2;\r
 194                                 bb1=bb1<<1;                             \r
 195                         }\r
 196                         //CHanel A\r
 197                         if (pack.convc1&1) {\r
 198                                 if (pack.CSA2&0x01)     ADMUX=0; else ADMUX=0x80;\r
 199                                 _delay_us(100);\r
 200                                 ADCSRA|=(1<<ADSC);\r
 201                                 while ((ADCSRA&(1<<ADSC)));\r
 202                                 cli();pack.A=ADC;sei();\r
 203                                 alarmflag=0;\r
 204                                 if (pack.CSA2&0x08)  //AEH\r
 205                                         if (pack.bytes[1]>pack.HA) {alarmflag=1;pack.CSA2|=0x20;}\r
 206                                 if (pack.CSA2&0x04)  //AEL\r
 207                                         if (pack.bytes[1]<pack.LA) {alarmflag=1;pack.CSA2|=0x10;}\r
 208                         }\r
 209 \r
 210                         if (pack.convc1&2) {\r
 211                                 if (pack.CSB2&0x01)     ADMUX=1; else ADMUX=0x81;\r
 212                                 _delay_us(100);\r
 213                                 ADCSRA|=(1<<ADSC);\r
 214                                 while ((ADCSRA&(1<<ADSC)));\r
 215                                 cli();pack.B=ADC;sei();\r
 216                                 if (pack.CSB2&0x08)  //AEH\r
 217                                         if (pack.bytes[1]>pack.HB) {alarmflag=1;pack.CSB2|=0x20;}\r
 218                                 if (pack.CSB2&0x04)  //AEL\r
 219                                         if (pack.bytes[1]<pack.LB) {alarmflag=1;pack.CSB2|=0x10;}\r
 220                         }\r
 221 \r
 222                         if (pack.convc1&4) {\r
 223                                 if (pack.CSC2&0x01)     ADMUX=2; else ADMUX=0x82;\r
 224                                 _delay_us(100);\r
 225                                 ADCSRA|=(1<<ADSC);\r
 226                                 while ((ADCSRA&(1<<ADSC)));\r
 227                                 cli();pack.C=ADC;sei();\r
 228                                 if (pack.CSC2&0x08)  //AEH\r
 229                                         if (pack.bytes[1]>pack.HC) {alarmflag=1;pack.CSC2|=0x20;}\r
 230                                 if (pack.CSC2&0x04)  //AEL\r
 231                                         if (pack.bytes[1]<pack.LC) {alarmflag=1;pack.CSC2|=0x10;}\r
 232                         } \r
 233                         if (pack.convc1&8) {\r
 234                                 if (pack.CSD2&0x01)     ADMUX=3; else ADMUX=0x83;\r
 235                                 _delay_us(100);\r
 236                                 ADCSRA|=(1<<ADSC);\r
 237                                 while ((ADCSRA&(1<<ADSC)));\r
 238                                 cli();pack.D=ADC;sei();\r
 239                                 if (pack.CSD2&0x08)  //AEH\r
 240                                         if (pack.bytes[1]>pack.HD) {alarmflag=1;pack.CSD2|=0x20;}\r
 241                                 if (pack.CSD2&0x04)  //AEL\r
 242                                         if (pack.bytes[1]<pack.LD) {alarmflag=1;pack.CSD2|=0x10;}\r
 243                         }\r
 244                         \r
 245                         EXTERN_SLEEP();\r
 246                         //PORTB&=~(1<<PINB1);\r
 247                 }\r
 248 \r
 249                 uint8_t bb=1;\r
 250                 for(volatile uint8_t i=0;i<4;i++) {\r
 251                         if (pack.bytes[8+i*2]&0x80) {  //Chanel as output\r
 252                                 if (pack.bytes[8+i*2]&0x40) {\r
 253                                 //      AD_DDR|=bb;\r
 254                                 } else {\r
 255                                         cli();\r
 256                                 //      AD_DDR&=~bb;\r
 257                                         sei();\r
 258                                 }\r
 259                         } else {\r
 260                                 cli();\r
 261                         //      AD_DDR&=~bb;\r
 262                                 sei();\r
 263                         }\r
 264                         bb=bb*2;\r
 265                 }\r
 266                 \r
 267 \r
 268 #if defined(__AVR_ATmega168__)||defined(__AVR_ATmega168A__)  ||defined(__AVR_ATmega328__) ||defined(__AVR_ATmega328P__) ||defined(__AVR_ATmega328PB__) \r
 269         if (((TIMSK0 & (1<<TOIE0))==0)&& (mode==0)){\r
 270         //if ( mode==0){\r
 271                 SMCR|=(1<<SE)|(1<<SM1);\r
 272                 EICRA&=~(1<<ISC01);\r
 273         } else {\r
 274                 SMCR|=(1<<SE);\r
 275                 SMCR&=~(1<<SM1);\r
 276         }\r
 277         asm("SLEEP");\r
 278 #else\r
 279 \r
 280 #if  defined(__AVR_ATtiny25__)||defined(__AVR_ATtiny45__)  || defined(__AVR_ATtiny85__)\r
 281                         if (((TIMSK & (1<<TOIE0))==0)&& (mode==0))\r
 282 #endif                  \r
 283 #if  defined(__AVR_ATtiny24__)||defined(__AVR_ATtiny44__)  || defined(__AVR_ATtiny84__) ||defined(__AVR_ATtiny24A__)||defined(__AVR_ATtiny44A__)  || defined(__AVR_ATtiny84A__) \r
 284                         if (((TIMSK0 & (1<<TOIE0))==0)&& (mode==0))\r
 285 #endif\r
 286                           {\r
 287 \r
 288                         MCUCR|=(1<<SE)|(1<<SM1);\r
 289                         MCUCR&=~(1<<SM0);\r
 290                         MCUCR&=~(1<<ISC01);\r
 291                 } else {\r
 292                         MCUCR|=(1<<SE);\r
 293                         MCUCR&=~(1<<SM1);\r
 294                 }\r
 295                 asm("SLEEP");\r
 296 #endif\r
 297    }\r
 298 \r
 299 \r
 300 }