1 // Copyright (c) 2017, Tobias Mueller tm(at)tm3d.de
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2 // All rights reserved.
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4 // Redistribution and use in source and binary forms, with or without
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5 // modification, are permitted provided that the following conditions are
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8 // * Redistributions of source code must retain the above copyright
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9 // notice, this list of conditions and the following disclaimer.
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10 // * Redistributions in binary form must reproduce the above copyright
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11 // notice, this list of conditions and the following disclaimer in the
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12 // documentation and/or other materials provided with the
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14 // * All advertising materials mentioning features or use of this
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15 // software must display the following acknowledgement: This product
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16 // includes software developed by tm3d.de and its contributors.
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17 // * Neither the name of tm3d.de nor the names of its contributors may
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18 // be used to endorse or promote products derived from this software
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19 // without specific prior written permission.
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21 // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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22 // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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23 // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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24 // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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25 // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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26 // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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27 // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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28 // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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29 // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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30 // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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31 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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33 #define F_CPU 8000000UL
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35 #include <avr/interrupt.h>
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36 #include <util/delay.h>
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37 #include <avr/wdt.h>
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38 #include <avr/sleep.h>
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39 #include <avr/pgmspace.h>
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40 #include "../common/I2C/USI_TWI_Master.h"
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41 #include "../common/I2C/BMP280.h"
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42 extern void OWINIT();
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43 extern void EXTERN_SLEEP();
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45 uint8_t owid[8]={0x20, 0xA2, 0xD9, 0x84, 0x00, 0x16, 0x02, 0x5D};/**/
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46 uint8_t config_info[26]={0x02,16,0x01,14, 0,0, 0x0,0,0x02,14,14,0x00,0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00};
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48 #error "Variable not correct"
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51 extern uint8_t mode;
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52 extern uint8_t gcontrol;
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53 extern uint8_t reset_indicator;
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54 extern uint8_t alarmflag;
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55 volatile uint8_t wdcounter=10;
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58 #if defined(__AVR_ATtiny24__)||defined(__AVR_ATtiny44__) || defined(__AVR_ATtiny84__) || defined(__AVR_ATtiny24A__)||defined(__AVR_ATtiny44A__) || defined(__AVR_ATtiny84A__)
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59 ISR(WATCHDOG_vect) {
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64 if (reset_indicator==1) reset_indicator++;
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65 else if (reset_indicator==2) mode=0;
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69 volatile uint8_t bytes[0x20];
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109 volatile pack_t pack;
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113 volatile int16_t am2302_temp;
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114 volatile uint16_t am2302_hum;
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117 uint8_t userRegister[1];
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119 volatile double temperatureC,humidityRH;
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148 PORTB=0xFF-(1<<PORTB0); //Schalter kann gegen Masse sein und zieht dann immer Strom
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149 DDRB|=(1<<PORTB0); //Als Ausgang und 0
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150 PORTA=0xFF; //All Pull up;
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151 PRR|=(1<<PRADC); // adc for save Power
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153 ACSR|=(1<<ACD); //Disable Comparator
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156 MCUCR &=~(1<<PUD); //All Pins Pullup...
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158 WDTCSR |= ((1<<WDCE) ); // Enable the WD Change Bit//| (1<<WDE)
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159 WDTCSR |= (1<<WDIE) | // Enable WDT Interrupt
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160 (1<<WDP3) | (1<<WDP0); // Set Timeout to ~8 seconds
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164 USI_TWI_Master_Initialise();
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169 //DDRB|=(1<<PINB1);
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173 if (wdcounter>3) {
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174 bmp280ConvertInt(&t,&P,1);
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185 //PORTB|=(1<<PINB1);
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188 for(uint8_t i=0;i<4;i++){
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189 if (pack.convc1&bb1) {
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190 if (pack.convc2&(bb)) {pack.bytes[i*2]=0;pack.bytes[i*2+1]=0;}
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192 if (pack.convc2&(bb)) {pack.bytes[i*2]=0xFF;pack.bytes[i*2+1]=0xFF;}
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198 if (pack.convc1&1) {
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199 /*if (pack.CSA2&0x01) ADMUX=0; else ADMUX=0x80;
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202 while ((ADCSRA&(1<<ADSC)));
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203 cli();pack.A=ADC;sei();*/
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204 cli();pack.A=P/100.0*32.0;sei();
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207 if (pack.CSA2&0x08) //AEH
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208 if (pack.bytes[1]>pack.HA) {alarmflag=1;pack.CSA2|=0x20;}
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209 if (pack.CSA2&0x04) //AEL
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210 if (pack.bytes[1]<pack.LA) {alarmflag=1;pack.CSA2|=0x10;}
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213 if (pack.convc1&2) {
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214 /*if (pack.CSB2&0x01) ADMUX=1; else ADMUX=0x81;
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217 while ((ADCSRA&(1<<ADSC)));
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218 cli();pack.B=ADC;sei();*/
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220 uint16_t ct=(t)+32767;
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221 cli();pack.B=ct;sei();
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222 if (pack.CSB2&0x08) //AEH
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223 if (pack.bytes[1]>pack.HB) {alarmflag=1;pack.CSB2|=0x20;}
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224 if (pack.CSB2&0x04) //AEL
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225 if (pack.bytes[1]<pack.LB) {alarmflag=1;pack.CSB2|=0x10;}
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228 if (pack.convc1&4) {
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229 /*if (pack.CSC2&0x01) ADMUX=2; else ADMUX=0x82;
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232 while ((ADCSRA&(1<<ADSC)));
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233 cli();pack.C=ADC;sei();*/
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235 cli();pack.C=0;sei();
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236 if (pack.CSC2&0x08) //AEH
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237 if (pack.bytes[1]>pack.HC) {alarmflag=1;pack.CSC2|=0x20;}
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238 if (pack.CSC2&0x04) //AEL
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239 if (pack.bytes[1]<pack.LC) {alarmflag=1;pack.CSC2|=0x10;}
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241 if (pack.convc1&8) {
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242 /*if (pack.CSD2&0x01) ADMUX=3; else ADMUX=0x83;
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245 while ((ADCSRA&(1<<ADSC)));
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246 cli();pack.D=ADC;sei();*/
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248 cli();pack.D=0;sei();
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249 if (pack.CSD2&0x08) //AEH
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250 if (pack.bytes[1]>pack.HD) {alarmflag=1;pack.CSD2|=0x20;}
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251 if (pack.CSD2&0x04) //AEL
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252 if (pack.bytes[1]<pack.LD) {alarmflag=1;pack.CSD2|=0x10;}
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256 //PORTB&=~(1<<PINB1);
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260 for(uint8_t i=0;i<4;i++) {
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261 if (pack.bytes[8+i*2]&0x80) { //Chanel as output
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262 if (pack.bytes[8+i*2]&0x40) {
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273 #if defined(__AVR_ATtiny25__)||defined(__AVR_ATtiny45__) || defined(__AVR_ATtiny85__)
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274 if (((TIMSK & (1<<TOIE0))==0)&& (mode==0))
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276 #if defined(__AVR_ATtiny24__)||defined(__AVR_ATtiny44__) || defined(__AVR_ATtiny84__) ||defined(__AVR_ATtiny24A__)||defined(__AVR_ATtiny44A__) || defined(__AVR_ATtiny84A__)
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277 if (((TIMSK0 & (1<<TOIE0))==0)&& (mode==0))
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281 MCUCR|=(1<<SE)|(1<<SM1);
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282 MCUCR&=~(1<<ISC01);
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