DS2450_IAQCORE/DS2450_IAQCORE.c

   1
   2 // Copyright (c) 2017, Tobias Mueller tm(at)tm3d.de
   3 // All rights reserved.
   4 //
   5 // Redistribution and use in source and binary forms, with or without
   6 // modification, are permitted provided that the following conditions are
   7 // met:
   8 //
   9 //  * Redistributions of source code must retain the above copyright
  10 //    notice, this list of conditions and the following disclaimer.
  11 //  * Redistributions in binary form must reproduce the above copyright
  12 //    notice, this list of conditions and the following disclaimer in the
  13 //    documentation and/or other materials provided with the
  14 //    distribution.
  15 //  * All advertising materials mentioning features or use of this
  16 //    software must display the following acknowledgement: This product
  17 //    includes software developed by tm3d.de and its contributors.
  18 //  * Neither the name of tm3d.de nor the names of its contributors may
  19 //    be used to endorse or promote products derived from this software
  20 //    without specific prior written permission.
  21 //
  22 // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  23 // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  24 // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  25 // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  26 // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  27 // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  28 // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  29 // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  30 // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  31 // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  32 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  33
  34 #define F_CPU 8000000UL
  35 #include <avr/io.h>
  36 #include <avr/interrupt.h>
  37 #include <util/delay.h>
  38 #include <avr/wdt.h>
  39 #include <avr/sleep.h>
  40 #include <avr/pgmspace.h>
  41 #include "../common/I2C/USI_TWI_Master.h"
  42 #include "../common/I2C/IAQCORE.h"
  43
  44 extern void OWINIT();
  45 extern void EXTERN_SLEEP();
  46
  47 uint8_t owid[8]={0x20, 0xA2, 0xD9, 0x84, 0x00, 0x16, 0x02, 0x5D};/**/
  48 uint8_t config_info[26]={0x06,13,0x06,13,0x06,13,0x06,13,0x02,20,20,20,20,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00};
  49
  50 #if (owid>128)
  51 #error "Variable not correct"
  52 #endif
  53
  54 extern uint8_t mode;
  55 extern uint8_t gcontrol;
  56 extern uint8_t reset_indicator;
  57 extern uint8_t alarmflag;
  58
  59
  60 typedef union {
  61         volatile uint8_t bytes[0x20];
  62         struct {
  63                 //Page0
  64                 uint16_t A;  //0
  65                 uint16_t B;  //2
  66                 uint16_t C;  //4
  67                 uint16_t D;  //6
  68                 //Page1
  69                 uint8_t CSA1;
  70                 uint8_t CSA2;
  71                 uint8_t CSB1;
  72                 uint8_t CSB2;
  73                 uint8_t CSC1;
  74                 uint8_t CSC2;
  75                 uint8_t CSD1;
  76                 uint8_t CSD2;
  77                 //Page2
  78                 uint8_t LA;
  79                 uint8_t HA;
  80                 uint8_t LB;
  81                 uint8_t HB;
  82                 uint8_t LC;
  83                 uint8_t HC;
  84                 uint8_t LD;
  85                 uint8_t HD;
  86                 //Page3
  87                 uint8_t FC1;
  88                 uint8_t FC2;
  89                 uint8_t FC3;
  90                 uint8_t FC4;
  91                 uint8_t VCCP;
  92                 uint8_t FC5;
  93                 uint8_t FC6;
  94                 uint8_t FC7;
  95                 uint8_t convc1;
  96                 uint8_t convc2;
  97
  98
  99         };
 100 } pack_t;
 101 volatile pack_t pack;
 102
 103
 104
 105 IAQCORE_Data_t IAQCORE_Data;
 106
 107
 108 int main(void){
 109         pack.A=0;
 110         pack.B=0;
 111         pack.C=0;
 112         pack.D=0;
 113         pack.CSA1=0x08;
 114         pack.CSA2=0x8C;
 115         pack.CSB1=0x08;
 116         pack.CSB2=0x8C;
 117         pack.CSC1=0x08;
 118         pack.CSC2=0x8C;
 119         pack.CSD1=0x08;
 120         pack.CSD2=0x8C;
 121         pack.HA=0xFF;
 122         pack.LA=0x00;
 123         pack.HB=0xFF;
 124         pack.LB=0x00;
 125         pack.HC=0xFF;
 126         pack.LC=0x00;
 127         pack.HD=0xFF;
 128         pack.LD=0x00;
 129         pack.VCCP=0;
 130         OWINIT();
 131
 132         MCUCR &=~(1<<PUD); //All Pins Pullup...
 133         MCUCR |=(1<<BODS);
 134         PORTA&=~((1<<PINA0)|(1<<PINA1)|(1<<PINA2)|(1<<PINA3));
 135         ADCSRA=(1<<ADEN)|(1<ADPS0)|(1<<ADPS2);
 136
 137
 138
 139         gcontrol=1;
 140         USI_TWI_Master_Initialise();
 141         ADCSRB|=(1<<ADLAR);
 142         sei();
 143
 144         //DDRB|=(1<<PINB1);
 145
 146     while(1)   {
 147
 148
 149                 if (gcontrol) {
 150                         readIAQCORE(&IAQCORE_Data);
 151                         //PORTB|=(1<<PINB1);
 152                         uint8_t bb=1;
 153                         uint8_t bb1=1;
 154                         for(uint8_t i=0;i<4;i++){
 155                                 if (pack.convc1&bb1) {
 156                                         if (pack.convc2&(bb)) {pack.bytes[i*2]=0;pack.bytes[i*2+1]=0;}
 157                                         bb=bb<<1;
 158                                         if (pack.convc2&(bb)) {pack.bytes[i*2]=0xFF;pack.bytes[i*2+1]=0xFF;}
 159                                         bb=bb<<1;
 160                                 } else bb=bb<<2;
 161                                 bb1=bb1<<1;
 162                         }
 163                         //CHanel A
 164                         if (pack.convc1&1) {
 165                                 cli();pack.A=IAQCORE_Data.CO2;sei();
 166                                 alarmflag=0;
 167                                 if (pack.CSA2&0x08)  //AEH
 168                                         if (pack.bytes[1]>pack.HA) {alarmflag=1;pack.CSA2|=0x20;}
 169                                 if (pack.CSA2&0x04)  //AEL
 170                                         if (pack.bytes[1]<pack.LA) {alarmflag=1;pack.CSA2|=0x10;}
 171                         }
 172
 173                         if (pack.convc1&2) {
 174                                 cli();pack.B=IAQCORE_Data.TVOC;sei();
 175                                 if (pack.CSB2&0x08)  //AEH
 176                                         if (pack.bytes[1]>pack.HB) {alarmflag=1;pack.CSB2|=0x20;}
 177                                 if (pack.CSB2&0x04)  //AEL
 178                                         if (pack.bytes[1]<pack.LB) {alarmflag=1;pack.CSB2|=0x10;}
 179                         }
 180
 181                         if (pack.convc1&4) {
 182                                 cli();pack.C=IAQCORE_Data.resistance/1000;sei();
 183                                 if (pack.CSC2&0x08)  //AEH
 184                                         if (pack.bytes[1]>pack.HC) {alarmflag=1;pack.CSC2|=0x20;}
 185                                 if (pack.CSC2&0x04)  //AEL
 186                                         if (pack.bytes[1]<pack.LC) {alarmflag=1;pack.CSC2|=0x10;}
 187                         }
 188                         if (pack.convc1&8) {
 189                                 cli();pack.D=IAQCORE_Data.state;sei();
 190                                 if (pack.CSD2&0x08)  //AEH
 191                                         if (pack.bytes[1]>pack.HD) {alarmflag=1;pack.CSD2|=0x20;}
 192                                 if (pack.CSD2&0x04)  //AEL
 193                                         if (pack.bytes[1]<pack.LD) {alarmflag=1;pack.CSD2|=0x10;}
 194                         }
 195
 196                         EXTERN_SLEEP();
 197                         //PORTB&=~(1<<PINB1);
 198                 }
 199
 200                 uint8_t bb=1;
 201                 for(uint8_t i=0;i<4;i++) {
 202                         if (pack.bytes[8+i*2]&0x80) {  //Chanel as output
 203                                 if (pack.bytes[8+i*2]&0x40) {
 204                                         DDRA|=bb;
 205                                 } else {
 206                                         DDRA&=~bb;
 207                                 }
 208                         } else {
 209                                 DDRA&=~bb;
 210                         }
 211                         bb=bb*2;
 212                 }
 213
 214 #if  defined(__AVR_ATtiny25__)||defined(__AVR_ATtiny45__)  || defined(__AVR_ATtiny85__)
 215                         if (((TIMSK & (1<<TOIE0))==0)&& (mode==0))
 216 #endif
 217 #if  defined(__AVR_ATtiny24__)||defined(__AVR_ATtiny44__)  || defined(__AVR_ATtiny84__) ||defined(__AVR_ATtiny24A__)||defined(__AVR_ATtiny44A__)  || defined(__AVR_ATtiny84A__)
 218                         if (((TIMSK0 & (1<<TOIE0))==0)&& (mode==0))
 219 #endif
 220                           {
 221
 222                         MCUCR|=(1<<SE)|(1<<SM1);
 223                         MCUCR&=~(1<<ISC01);
 224                 } else {
 225                         MCUCR|=(1<<SE);
 226                         MCUCR&=~(1<<SM1);
 227                 }
 228         //      asm("SLEEP");
 229    }
 230
 231
 232 }