2 // Copyright (c) 2018, Tobias Mueller tm(at)tm3d.de
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3 // All rights reserved.
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5 // Redistribution and use in source and binary forms, with or without
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6 // modification, are permitted provided that the following conditions are
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9 // * Redistributions of source code must retain the above copyright
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10 // notice, this list of conditions and the following disclaimer.
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11 // * Redistributions in binary form must reproduce the above copyright
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12 // notice, this list of conditions and the following disclaimer in the
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13 // documentation and/or other materials provided with the
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15 // * All advertising materials mentioning features or use of this
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16 // software must display the following acknowledgement: This product
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17 // includes software developed by tm3d.de and its contributors.
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18 // * Neither the name of tm3d.de nor the names of its contributors may
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19 // be used to endorse or promote products derived from this software
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20 // without specific prior written permission.
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22 // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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23 // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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24 // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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25 // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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26 // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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27 // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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28 // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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29 // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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30 // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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31 // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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32 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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34 #define _CHANGEABLE_ID_
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35 #define _ZERO_POLLING_
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36 #define _HANDLE_CC_COMMAND_
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37 #include "../common/OWConfig.s"
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38 #include "../common/OWCRC8_16.s"
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43 .comm addr,1 ;zweites Adressbyte ist unnoetig (Warum auch immer fuer 32 Byte 16 Bit Adressen verwendet werden....)
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44 .comm crcsave,1 ; zwischenspeicherspeicher fuer crc nur zweites byte....
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45 //.extern am2302_temp,2
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46 .comm stat_to_sample,1
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48 .comm block,1 ; Block der augegeben, geschrieben wird (Parameter von READ/WRITE Scratchpad)
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49 .comm cpsp,1 ; Copy Scratchpad marker
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51 .macro CHIP_INIT ;r_temp is pushed other Registers should be saved
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57 sbic _SFR_IO_ADDR(EECR), EEPE
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58 rjmp Init_EEPROM_read
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60 out _SFR_IO_ADDR(EEARH), r_temp
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62 out _SFR_IO_ADDR(EEARL), r_temp
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63 sbi _SFR_IO_ADDR(EECR), EERE
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64 in r_temp,_SFR_IO_ADDR(EEDR)
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66 rcall hrc_recall_eeprom_func1
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72 .macro COMMAND_TABLE
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73 rjmp h_readscratchpad1
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74 rjmp h_writescratchpad1
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76 rjmp h_readpioregaddr2
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78 rjmp h_readpioregcrc12
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79 rjmp h_readpioregcrc22
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81 rjmp h_readchanel_crc2
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83 rjmp h_writecomchanel2
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85 rjmp h_writesendchanel2
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86 rjmp h_resetactivity2
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87 rjmp h_writeregaddr2
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91 #include "../common/OWRomFunctionsDual.s"
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92 #include "../common/OWTimerInterrupt.s"
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96 ; Ab hier Geraeteabhaenging
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98 #define OW_READ_SCRATCHPAD1 OW_FIRST_COMMAND+0
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99 #define OW_WRITE_SCRATCHPAD1 OW_FIRST_COMMAND+1
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100 #define OW_CONVERT_RUN1 OW_FIRST_COMMAND+2
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102 #define OW_READ_PIO_REG_ADDR2 OW_FIRST_COMMAND+3
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103 #define OW_READ_PIO_REG2 OW_FIRST_COMMAND+4
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104 #define OW_READ_PIO_REG_CRC12 OW_FIRST_COMMAND+5
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105 #define OW_READ_PIO_REG_CRC22 OW_FIRST_COMMAND+6
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106 #define OW_READ_CHANEL2 OW_FIRST_COMMAND+7
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107 #define OW_READ_CHANEL_CRC2 OW_FIRST_COMMAND+8
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108 #define OW_WRITE_CHANEL2 OW_FIRST_COMMAND+9
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109 #define OW_WRITE_COMCHANEL2 OW_FIRST_COMMAND+10
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110 #define OW_WRITE_SENDAA2 OW_FIRST_COMMAND+11
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111 #define OW_WRITE_SEND_CHANEL2 OW_FIRST_COMMAND+12
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112 #define OW_RESET_ACTIVITY2 OW_FIRST_COMMAND+13
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113 #define OW_WRITE_REG_ADDR2 OW_FIRST_COMMAND+14
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114 #define OW_WRITE_REG2 OW_FIRST_COMMAND+15
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116 ;---------------------------------------------------
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117 ; READ COMMAND and start operation
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118 ;---------------------------------------------------
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120 #ifdef _HANDLE_CC_COMMAND_
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123 cjmp 0x44,hrc_set_convertT12
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124 ldi r_mode,OW_SLEEP
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131 #ifndef _DIS_FLASH_
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132 FLASH_COMMANDS ; muss zu erst sein....
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134 cjmp 0xBE,hrc_set_readscratchpad1
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135 cjmp 0x4E,hrc_set_writescratchpad1
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136 cjmp 0x44,hrc_set_convertT1
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137 cjmp 0x48,hrc_copy_scratchpad1
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138 cjmp 0xB8,hrc_recall_eeprom1
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140 #ifdef _CHANGEABLE_ID_
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143 ldi r_mode,OW_SLEEP
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146 hrc_set_readscratchpad1:
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147 ldi r_mode,OW_READ_SCRATCHPAD1
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150 rjmp h_readscratchpad1
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152 hrc_set_writescratchpad1:
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153 ldi r_mode,OW_WRITE_SCRATCHPAD1
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154 ldi r_bytep,2 ;start to write in 2
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157 hrc_recall_eeprom1:
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158 rcall hrc_recall_eeprom_func1
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161 #ifdef _HANDLE_CC_COMMAND_
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162 hrc_set_convertT12:
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163 rjmp hrc_set_convertT1
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168 sts gcontrol,r_temp
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169 hrc_set_convertT12b:
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170 ldi r_mode,OW_CONVERT_RUN1
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171 ldi r_sendflag,3 ;set bit 0 and 1 for no zero polling
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175 rjmp handle_end_no_bcount
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179 hrc_copy_scratchpad1:
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181 configZ pack1,r_bytep
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183 hrc_copy_scratchpad_EEPROM_write1:
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184 sbic _SFR_IO_ADDR(EECR), EEPE
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185 rjmp hrc_copy_scratchpad_EEPROM_write1
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186 ldi r_temp, (0<<EEPM1)|(0<<EEPM0)
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187 out _SFR_IO_ADDR(EECR), r_temp
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189 out _SFR_IO_ADDR(EEARH),r_temp
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190 out _SFR_IO_ADDR(EEARL), r_bytep
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192 out _SFR_IO_ADDR(EEDR), r_rwbyte
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193 sbi _SFR_IO_ADDR(EECR), EEMPE
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194 sbi _SFR_IO_ADDR(EECR), EEPE
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197 brne hrc_copy_scratchpad_EEPROM_write1
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201 hrc_recall_eeprom_func1:
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203 configZ pack1,r_bytep
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206 hrc_recall_eeprom_EEPROM_read1:
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207 sbic _SFR_IO_ADDR(EECR), EEPE
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208 rjmp hrc_recall_eeprom_EEPROM_read1
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209 out _SFR_IO_ADDR(EEARH), r_temp
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210 out _SFR_IO_ADDR(EEARL), r_bytep
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211 sbi _SFR_IO_ADDR(EECR), EERE
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212 in r_rwbyte,_SFR_IO_ADDR(EEDR)
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216 brne hrc_recall_eeprom_EEPROM_read1
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224 ;---------------------------------------------------
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226 ;---------------------------------------------------
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230 breq h_readscratchpad_crc1
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232 breq h_readscratchpad_all1
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233 configZ pack1,r_bytep
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235 rjmp h_readscratchpad_endc1
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236 h_readscratchpad_crc1:
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238 h_readscratchpad_endc1:
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242 h_readscratchpad_all1:
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243 rjmp handle_end_sleep
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249 ;---------------------------------------------------
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251 ;---------------------------------------------------
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253 h_writescratchpad1:
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254 configZ pack1,r_bytep
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257 breq h_writescratchpad_all1
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260 h_writescratchpad_all1:
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261 ;ori r_rwbyte,0x1F ; Alle unteren Bits sind immer 1 -->VOC use different
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263 rjmp handle_end_sleep
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265 ;*****************************************************************************************************************************************************************************************
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266 ;*****************************************************************************************************************************************************************************************
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267 ;*****************************************************************************************************************************************************************************************
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268 ;*****************************************************************************************************************************************************************************************
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269 ;*****************************************************************************************************************************************************************************************
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295 #ifndef _DIS_FLASH_
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296 FLASH_COMMANDS ; muss zu erst sein....
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298 cset 0xF0,OW_READ_PIO_REG_ADDR2
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299 cljmp 0xF5,hrc_readchanel2
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300 cset 0x5A,OW_WRITE_CHANEL2
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301 cljmp 0xC3,hrc_reset_activity2
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302 cset 0xCC,OW_WRITE_REG_ADDR2
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304 #ifdef _CHANGEABLE_ID_
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307 ldi r_mode,OW_SLEEP
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312 cpi r_bytep,0 ;erstes Adressbyte ?
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313 brne h_readpioreg_addr_byte12 ;nein dann weiter
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314 //andi r_rwbyte,0x1F ; nur Adressen zwischen 0 und 0x1F zulassen
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315 subi r_rwbyte,0x89 ;beim lesen von 0x88 --> 0xFF inc addr -> 0x00
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316 sts addr,r_rwbyte ;speichern des ersten bytes
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317 rjmp handle_end_inc
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318 h_readpioreg_addr_byte12: ;zweiters Addressbyte wird nicht gespeichert!
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319 ldi r_mode,OW_READ_PIO_REG2 ;weiter zu read Memory
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320 ;;ldi r_bcount,1 ;ist unten
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321 ldi r_sendflag,1 ;jetzt sendet der Slave zum Master
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328 breq h_readpioreg_init_crc2
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329 brge h_readpioreg_end2 ; groeser dann nix senden
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330 configZ pack2,r_bytep
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333 rjmp handle_end ;sendet das Byte und geht zu h_readmemory
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334 h_readpioreg_init_crc2:; init erstes CRC byte
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340 ldi r_mode,OW_READ_PIO_REG_CRC12
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344 ldi r_mode,OW_SLEEP
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347 h_readpioregcrc12:;init zweites CRC Byte
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348 lds r_rwbyte,crcsave
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350 ldi r_mode,OW_READ_PIO_REG_CRC22
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352 h_readpioregcrc22: ; 2. CRC Byte gesendet
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353 rjmp h_readpioreg_end2
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357 ldi r_sendflag,1 ;jetzt sendet der Slave zum Master
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358 ldi r_mode,OW_READ_CHANEL2
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360 sts gcontrol,r_temp
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361 rjmp h_readchanel12
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364 sts gcontrol,r_temp
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367 brge h_readchanelcrc12
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368 lds r_rwbyte,stat_to_sample
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369 sts pack2,r_rwbyte //sample
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370 rjmp handle_end_inc
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377 ldi r_mode,OW_READ_CHANEL_CRC2
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382 ldi r_mode,OW_READ_CHANEL2
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383 lds r_rwbyte,crcsave
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387 sts crcsave,r_rwbyte
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388 ldi r_mode,OW_WRITE_COMCHANEL2
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395 rjmp handle_end_sleep
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397 sts pack2+1,r_rwbyte
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399 sts gcontrol,r_temp2
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402 ldi r_mode,OW_WRITE_SENDAA2
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403 ldi r_sendflag,1 ;jetzt sendet der Slave zum Master
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407 ldi r_mode,OW_WRITE_SEND_CHANEL2
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409 h_writesendchanel2:
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410 rjmp handle_end_sleep
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414 hrc_reset_activity2:
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416 sts gcontrol,r_temp
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418 ldi r_mode,OW_RESET_ACTIVITY2
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419 ldi r_sendflag,1 ;jetzt sendet der Slave zum Master
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422 rjmp handle_end_sleep
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426 cpi r_bytep,0 ;erstes Adressbyte ?
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427 brne h_writeregddr_byte12 ;nein dann weiter
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428 //andi r_rwbyte,0x1F ; nur Adressen zwischen 0 und 0x1F zulassen
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429 subi r_rwbyte,0x8B
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430 brmi h_writereg_end2
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431 sts addr,r_rwbyte ;speichern des ersten bytes
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432 rjmp handle_end_inc
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433 h_writeregddr_byte12: ;zweiters Addressbyte wird nicht gespeichert!
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434 ldi r_mode,OW_WRITE_REG2 ;weiter zu write Memory
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435 ;;ldi r_bcount,1 ;ist unten
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440 configZ pack2+3,r_temp
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443 brge h_writereg_end2
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446 rjmp handle_end_sleep
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449 rjmp handle_end_sleep
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455 #include "../common/OWPinInterrupt.s"
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