1 // Copyright (c) 2017, Tobias Mueller tm(at)tm3d.de
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2 // All rights reserved.
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4 // Redistribution and use in source and binary forms, with or without
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5 // modification, are permitted provided that the following conditions are
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8 // * Redistributions of source code must retain the above copyright
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9 // notice, this list of conditions and the following disclaimer.
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10 // * Redistributions in binary form must reproduce the above copyright
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11 // notice, this list of conditions and the following disclaimer in the
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12 // documentation and/or other materials provided with the
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14 // * All advertising materials mentioning features or use of this
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15 // software must display the following acknowledgement: This product
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16 // includes software developed by tm3d.de and its contributors.
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17 // * Neither the name of tm3d.de nor the names of its contributors may
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18 // be used to endorse or promote products derived from this software
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19 // without specific prior written permission.
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21 // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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22 // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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23 // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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24 // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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25 // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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26 // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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27 // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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28 // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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29 // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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30 // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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31 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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34 #define OW_PORT _SFR_IO_ADDR(PORTD) //1 Wire Port
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35 #define OW_PIN _SFR_IO_ADDR(PIND) //1 Wire Pin as number
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36 #define OW_PINN PORTD2
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37 #define OW_DDR _SFR_IO_ADDR(DDRD) //pin direction register
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39 #define TCNT_REG _SFR_IO_ADDR(TCNT0)
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42 #define DB_PORT _SFR_IO_ADDR(PORTB) //DEBUG
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43 #define DB_PIN _SFR_IO_ADDR(PINB) //DEBUG
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44 #define DB_DDR _SFR_IO_ADDR(DDRB) //DEBUG
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45 #define DB_PINN PORTB1
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47 #define SETZEROMARKER sbi _SFR_IO_ADDR(DDRC),6
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48 #define RESETZEROMARKER cbi _SFR_IO_ADDR(DDRC),6
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49 #define TESTZEROMARKER sbic _SFR_IO_ADDR(DDRC),6
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52 #define sdb sbi _SFR_IO_ADDR(PORTB),DB_PINN
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53 #define cdb cbi _SFR_IO_ADDR(PORTB),DB_PINN
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59 #define TIMER_INTERRUPT TIMER0_OVF_vect
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60 #define PIN_INTERRUPT INT0_vect
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63 //#define OWT_MIN_RESET 160
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64 //#define OWT_RESET2 40
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65 //#define OWT_RESET_PRESENT 15
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66 //#define OWT_PRESENT 50
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67 //#define OWT_WRITE 18
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68 //#define OWT_READ 4
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70 #define OWT_MIN_RESET 80
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71 #define OWT_RESET2 30
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72 #define OWT_RESET_PRESENT 15
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73 #define OWT_PRESENT 60
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74 #define OWT_WRITE 16
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76 #define OWT_ZP_WAIT_LOW_TO 36 ; Zeit fuer die Maximale Lowzeit bei der Zerro Polling pruefung. Ist die Leitung laenger low, ist es vieleicht ein Reset
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77 #define OWT_ZP_WAIT_HIGH_TO 54 ; Zeit fuer die Maximale Hight zeit bis zu einem Low Impuls vom Master. Nach laengeren Pausen wird nicht mehr gepollt sondern der Interrup vererndet.
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79 #define OWT_MIN_RESET 180
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80 #define OWT_RESET2 80
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81 #define OWT_RESET_PRESENT 30
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82 #define OWT_PRESENT 130
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83 #define OWT_WRITE 35
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85 #define OWT_ZP_WAIT_LOW_TO 60 ; Zeit fuer die Maximale Lowzeit bei der Zerro Polling pruefung. Ist die Leitung laenger low, ist es vieleicht ein Reset
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86 #define OWT_ZP_WAIT_HIGH_TO 90 ; Zeit fuer die Maximale Hight zeit bis zu einem Low Impuls vom Master. Nach laengeren Pausen wird nicht mehr gepollt sondern der Interrup vererndet.
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89 .macro CLEAR_TOV_FLAG
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91 out _SFR_IO_ADDR(TIFR0),r_temp
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95 in r_temp, _SFR_IO_ADDR(TIFR0)
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96 sbrc r_temp,TOV0 ; wenn ueberlauf gleich weiter
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99 .macro CLEAR_INTERRUPT_FLAG
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100 ldi r_temp,(1<<INTF0);inerrupt flags durch 1 loeschen..... 0 macht nix
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101 out _SFR_IO_ADDR(EIFR),r_temp
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105 ldi r_temp,(1<<TOIE0)
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107 ldi r_temp,(1<<TOV0) ;inerrupt flags durch 1 loeschen..... 0 macht nix
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108 out _SFR_IO_ADDR(TIFR0),r_temp
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116 //Wiederherstellen von Idle mode und umschalten von Low-Level interrupt zu Falling edge
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117 .macro SET_FALLING_RESET_SLEEP
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119 ori r_temp,(1<<ISC01)
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122 andi r_temp,~(1<<SM1)
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126 .macro HW_INIT ;r_temp is pushed other Registers should be saved
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127 ;set clock to 8 MHz
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130 //ldi r_temp,(1<<CLKPS0)
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139 sts TIMSK0,r_temp ;; is default
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141 ldi r_temp,(1<<INT0)
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142 out _SFR_IO_ADDR(EIMSK),r_temp
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143 ;Set Timerclock to Clock / 8 (2us bei 4MHz) bzw 1us bei 8 MHz
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144 ldi r_temp,(1<<CS01)
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145 out _SFR_IO_ADDR(TCCR0B),r_temp
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147 cbi OW_DDR,OW_PINN ;; is default....
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148 cbi OW_PORT,OW_PINN ;; vereinfachung im Hauptprogram (PORTB=0xFF) wegen pullup
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150 ldi r_temp,(1<<ISC01)
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162 ret ; Direkter Sprung zum Bootloader
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165 .macro CHECK_BOOTLOADER_PIN
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