DS2450_IAQCORE/DS2450_IAQCORE.c

   1 \r
   2 // Copyright (c) 2017, Tobias Mueller tm(at)tm3d.de\r
   3 // All rights reserved.\r
   4 //\r
   5 // Redistribution and use in source and binary forms, with or without\r
   6 // modification, are permitted provided that the following conditions are\r
   7 // met:\r
   8 //\r
   9 //  * Redistributions of source code must retain the above copyright\r
  10 //    notice, this list of conditions and the following disclaimer.\r
  11 //  * Redistributions in binary form must reproduce the above copyright\r
  12 //    notice, this list of conditions and the following disclaimer in the\r
  13 //    documentation and/or other materials provided with the\r
  14 //    distribution.\r
  15 //  * All advertising materials mentioning features or use of this\r
  16 //    software must display the following acknowledgement: This product\r
  17 //    includes software developed by tm3d.de and its contributors.\r
  18 //  * Neither the name of tm3d.de nor the names of its contributors may\r
  19 //    be used to endorse or promote products derived from this software\r
  20 //    without specific prior written permission.\r
  21 //\r
  22 // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\r
  23 // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\r
  24 // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\r
  25 // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\r
  26 // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\r
  27 // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
  28 // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\r
  29 // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\r
  30 // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\r
  31 // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
  32 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
  33 \r
  34 #define F_CPU 8000000UL\r
  35 #include <avr/io.h>\r
  36 #include <avr/interrupt.h>\r
  37 #include <util/delay.h>\r
  38 #include <avr/wdt.h>\r
  39 #include <avr/sleep.h>\r
  40 #include <avr/pgmspace.h>\r
  41 #include "../common/I2C/USI_TWI_Master.h"\r
  42 #include "../common/I2C/IAQCORE.h"\r
  43 \r
  44 extern void OWINIT();\r
  45 extern void EXTERN_SLEEP();\r
  46 \r
  47 uint8_t owid[8]={0x20, 0xA2, 0xD9, 0x84, 0x00, 0x16, 0x02, 0x5D};/**/\r
  48 uint8_t config_info[26]={10,13,8,13,11,13,5,13,0x02,27,27,27,27,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00};\r
  49 \r
  50 #if (owid>128) \r
  51 #error "Variable not correct"\r
  52 #endif\r
  53 \r
  54 extern uint8_t mode;\r
  55 extern uint8_t gcontrol;\r
  56 extern uint8_t reset_indicator;\r
  57 extern uint8_t alarmflag;\r
  58 \r
  59 \r
  60 typedef union {\r
  61         volatile uint8_t bytes[0x20];\r
  62         struct {\r
  63                 //Page0\r
  64                 uint16_t A;  //0\r
  65                 uint16_t B;  //2\r
  66                 uint16_t C;  //4\r
  67                 uint16_t D;  //6\r
  68                 //Page1\r
  69                 uint8_t CSA1;\r
  70                 uint8_t CSA2;\r
  71                 uint8_t CSB1;\r
  72                 uint8_t CSB2;\r
  73                 uint8_t CSC1;\r
  74                 uint8_t CSC2;\r
  75                 uint8_t CSD1;\r
  76                 uint8_t CSD2;\r
  77                 //Page2\r
  78                 uint8_t LA;\r
  79                 uint8_t HA;\r
  80                 uint8_t LB;\r
  81                 uint8_t HB;\r
  82                 uint8_t LC;\r
  83                 uint8_t HC;\r
  84                 uint8_t LD;\r
  85                 uint8_t HD;\r
  86                 //Page3\r
  87                 uint8_t FC1;\r
  88                 uint8_t FC2;\r
  89                 uint8_t FC3;\r
  90                 uint8_t FC4;\r
  91                 uint8_t VCCP;\r
  92                 uint8_t FC5;\r
  93                 uint8_t FC6;\r
  94                 uint8_t FC7;\r
  95                 uint8_t convc1;\r
  96                 uint8_t convc2;\r
  97                 \r
  98                 \r
  99         };\r
 100 } pack_t;\r
 101 volatile pack_t pack;\r
 102 \r
 103 \r
 104 \r
 105 IAQCORE_Data_t IAQCORE_Data;\r
 106 \r
 107 \r
 108 int main(void){\r
 109         pack.A=0;\r
 110         pack.B=0;\r
 111         pack.C=0;\r
 112         pack.D=0;\r
 113         pack.CSA1=0x08;\r
 114         pack.CSA2=0x8C;\r
 115         pack.CSB1=0x08;\r
 116         pack.CSB2=0x8C;\r
 117         pack.CSC1=0x08;\r
 118         pack.CSC2=0x8C;\r
 119         pack.CSD1=0x08;\r
 120         pack.CSD2=0x8C;\r
 121         pack.HA=0xFF;\r
 122         pack.LA=0x00;\r
 123         pack.HB=0xFF;\r
 124         pack.LB=0x00;\r
 125         pack.HC=0xFF;\r
 126         pack.LC=0x00;\r
 127         pack.HD=0xFF;\r
 128         pack.LD=0x00;\r
 129         pack.VCCP=0;\r
 130         OWINIT();\r
 131 \r
 132         MCUCR &=~(1<<PUD); //All Pins Pullup...\r
 133         MCUCR |=(1<<BODS);\r
 134         PORTA&=~((1<<PINA0)|(1<<PINA1)|(1<<PINA2)|(1<<PINA3));\r
 135         ADCSRA=(1<<ADEN)|(1<ADPS0)|(1<<ADPS2);\r
 136 \r
 137         \r
 138         \r
 139         gcontrol=1;\r
 140         USI_TWI_Master_Initialise();\r
 141         ADCSRB|=(1<<ADLAR); \r
 142         sei();\r
 143         \r
 144         //DDRB|=(1<<PINB1);\r
 145 \r
 146     while(1)   {\r
 147 \r
 148 \r
 149                 if (gcontrol) {\r
 150                         readIAQCORE(&IAQCORE_Data);\r
 151                         //PORTB|=(1<<PINB1);\r
 152                         uint8_t bb=1;\r
 153                         uint8_t bb1=1;\r
 154                         for(uint8_t i=0;i<4;i++){\r
 155                                 if (pack.convc1&bb1) {\r
 156                                         if (pack.convc2&(bb)) {pack.bytes[i*2]=0;pack.bytes[i*2+1]=0;}\r
 157                                         bb=bb<<1;\r
 158                                         if (pack.convc2&(bb)) {pack.bytes[i*2]=0xFF;pack.bytes[i*2+1]=0xFF;}\r
 159                                         bb=bb<<1;\r
 160                                 } else bb=bb<<2;\r
 161                                 bb1=bb1<<1;                             \r
 162                         }\r
 163                         //CHanel A\r
 164                         if (pack.convc1&1) {\r
 165                                 cli();pack.A=IAQCORE_Data.CO2;sei();\r
 166                                 alarmflag=0;\r
 167                                 if (pack.CSA2&0x08)  //AEH\r
 168                                         if (pack.bytes[1]>pack.HA) {alarmflag=1;pack.CSA2|=0x20;}\r
 169                                 if (pack.CSA2&0x04)  //AEL\r
 170                                         if (pack.bytes[1]<pack.LA) {alarmflag=1;pack.CSA2|=0x10;}\r
 171                         }\r
 172 \r
 173                         if (pack.convc1&2) {\r
 174                                 cli();pack.B=IAQCORE_Data.TVOC;sei();\r
 175                                 if (pack.CSB2&0x08)  //AEH\r
 176                                         if (pack.bytes[1]>pack.HB) {alarmflag=1;pack.CSB2|=0x20;}\r
 177                                 if (pack.CSB2&0x04)  //AEL\r
 178                                         if (pack.bytes[1]<pack.LB) {alarmflag=1;pack.CSB2|=0x10;}\r
 179                         }\r
 180 \r
 181                         if (pack.convc1&4) {\r
 182                                 cli();pack.C=IAQCORE_Data.resistance/1000;sei();\r
 183                                 if (pack.CSC2&0x08)  //AEH\r
 184                                         if (pack.bytes[1]>pack.HC) {alarmflag=1;pack.CSC2|=0x20;}\r
 185                                 if (pack.CSC2&0x04)  //AEL\r
 186                                         if (pack.bytes[1]<pack.LC) {alarmflag=1;pack.CSC2|=0x10;}\r
 187                         } \r
 188                         if (pack.convc1&8) {\r
 189                                 cli();pack.D=IAQCORE_Data.state;sei();\r
 190                                 if (pack.CSD2&0x08)  //AEH\r
 191                                         if (pack.bytes[1]>pack.HD) {alarmflag=1;pack.CSD2|=0x20;}\r
 192                                 if (pack.CSD2&0x04)  //AEL\r
 193                                         if (pack.bytes[1]<pack.LD) {alarmflag=1;pack.CSD2|=0x10;}\r
 194                         }\r
 195                         \r
 196                         EXTERN_SLEEP();\r
 197                         //PORTB&=~(1<<PINB1);\r
 198                 }\r
 199 \r
 200                 uint8_t bb=1;\r
 201                 for(uint8_t i=0;i<4;i++) {\r
 202                         if (pack.bytes[8+i*2]&0x80) {  //Chanel as output\r
 203                                 if (pack.bytes[8+i*2]&0x40) {\r
 204                                         DDRA|=bb;\r
 205                                 } else {\r
 206                                         DDRA&=~bb;\r
 207                                 }\r
 208                         } else {\r
 209                                 DDRA&=~bb;\r
 210                         }\r
 211                         bb=bb*2;\r
 212                 }\r
 213                 \r
 214 #if  defined(__AVR_ATtiny25__)||defined(__AVR_ATtiny45__)  || defined(__AVR_ATtiny85__)\r
 215                         if (((TIMSK & (1<<TOIE0))==0)&& (mode==0))\r
 216 #endif                  \r
 217 #if  defined(__AVR_ATtiny24__)||defined(__AVR_ATtiny44__)  || defined(__AVR_ATtiny84__) ||defined(__AVR_ATtiny24A__)||defined(__AVR_ATtiny44A__)  || defined(__AVR_ATtiny84A__)\r
 218                         if (((TIMSK0 & (1<<TOIE0))==0)&& (mode==0))\r
 219 #endif\r
 220                           {\r
 221 \r
 222                         MCUCR|=(1<<SE)|(1<<SM1);\r
 223                         MCUCR&=~(1<<ISC01);\r
 224                 } else {\r
 225                         MCUCR|=(1<<SE);\r
 226                         MCUCR&=~(1<<SM1);\r
 227                 }\r
 228         //      asm("SLEEP");\r
 229    }\r
 230 \r
 231 \r
 232 }