4 //********** Defines **********//
\r
6 // Defines controlling timing limits
\r
7 #define TWI_FAST_MODE
\r
9 #define SYS_CLK 4000.0 // [kHz]
\r
11 #define SYS_CLK 8000.0 // [kHz]
\r
16 #ifdef TWI_FAST_MODE // TWI FAST mode timing limits. SCL = 100-400kHz
\r
17 #define T2_TWI ((SYS_CLK *1300) /1000000) +1 // >1,3us
\r
18 #define T4_TWI ((SYS_CLK * 600) /1000000) +1 // >0,6us
\r
20 #else // TWI STANDARD mode timing limits. SCL <= 100kHz
\r
21 #define T2_TWI ((SYS_CLK *4700) /1000000) +1 // >4,7us
\r
22 #define T4_TWI ((SYS_CLK *4000) /1000000) +1 // >4,0us
\r
25 // Defines controling code generating
\r
26 //#define PARAM_VERIFICATION
\r
27 //#define NOISE_TESTING
\r
28 //#define SIGNAL_VERIFY
\r
30 //USI_TWI messages and flags and bit masks
\r
33 /****************************************************************************
\r
34 Bit and byte definitions
\r
35 ****************************************************************************/
\r
36 #define TWI_READ_BIT 0 // Bit position for R/W bit in "address byte".
\r
37 #define TWI_ADR_BITS 1 // Bit position for LSB of the slave address bits in the init byte.
\r
38 #define TWI_NACK_BIT 0 // Bit position for (N)ACK bit.
\r
40 #define USI_TWI_NO_DATA 0x00 // Transmission buffer is empty
\r
41 #define USI_TWI_DATA_OUT_OF_BOUND 0x01 // Transmission buffer is outside SRAM space
\r
42 #define USI_TWI_UE_START_CON 0x02 // Unexpected Start Condition
\r
43 #define USI_TWI_UE_STOP_CON 0x03 // Unexpected Stop Condition
\r
44 #define USI_TWI_UE_DATA_COL 0x04 // Unexpected Data Collision (arbitration)
\r
45 #define USI_TWI_NO_ACK_ON_DATA 0x05 // The slave did not acknowledge all data
\r
46 #define USI_TWI_NO_ACK_ON_ADDRESS 0x06 // The slave did not acknowledge the address
\r
47 #define USI_TWI_MISSING_START_CON 0x07 // Generated Start Condition not detected on bus
\r
48 #define USI_TWI_MISSING_STOP_CON 0x08 // Generated Stop Condition not detected on bus
\r
50 // Device dependant defines
\r
52 #if defined(__AVR_AT90Mega169__) | defined(__AVR_ATmega169PA__) | \
\r
53 defined(__AVR_AT90Mega165__) | defined(__AVR_ATmega165__) | \
\r
54 defined(__AVR_ATmega325__) | defined(__AVR_ATmega3250__) | \
\r
55 defined(__AVR_ATmega645__) | defined(__AVR_ATmega6450__) | \
\r
56 defined(__AVR_ATmega329__) | defined(__AVR_ATmega3290__) | \
\r
57 defined(__AVR_ATmega649__) | defined(__AVR_ATmega6490__)
\r
58 #define DDR_USI DDRE
\r
59 #define PORT_USI PORTE
\r
60 #define PIN_USI PINE
\r
61 #define PORT_USI_SDA PORTE5
\r
62 #define PORT_USI_SCL PORTE4
\r
63 #define PIN_USI_SDA PINE5
\r
64 #define PIN_USI_SCL PINE4
\r
67 #if defined(__AVR_ATtiny25__) | defined(__AVR_ATtiny45__) | defined(__AVR_ATtiny85__) | \
\r
68 defined(__AVR_AT90Tiny26__) | defined(__AVR_ATtiny26__)
\r
69 #define DDR_USI DDRB
\r
70 #define PORT_USI PORTB
\r
71 #define PIN_USI PINB
\r
72 #define PORT_USI_SDA PORTB0
\r
73 #define PORT_USI_SCL PORTB2
\r
74 #define PIN_USI_SDA PINB0
\r
75 #define PIN_USI_SCL PINB2
\r
78 #if defined(__AVR_AT90Tiny2313__) | defined(__AVR_ATtiny2313__)
\r
79 #define DDR_USI DDRB
\r
80 #define PORT_USI PORTB
\r
81 #define PIN_USI PINB
\r
82 #define PORT_USI_SDA PORTB5
\r
83 #define PORT_USI_SCL PORTB7
\r
84 #define PIN_USI_SDA PINB5
\r
85 #define PIN_USI_SCL PINB7
\r
88 #if defined(__AVR_ATtiny84__) | defined(__AVR_ATtiny84A__)
\r
89 #define DDR_USI DDRA
\r
90 #define PORT_USI PORTA
\r
91 #define PIN_USI PINA
\r
92 #define PORT_USI_SDA PORTA6
\r
93 #define PORT_USI_SCL PORTA4
\r
94 #define PIN_USI_SDA PINA6
\r
95 #define PIN_USI_SCL PINA4
\r
99 //****************** ATMEGA TWI without USI
\r
100 #define TWI_BUFFER_SIZE 4 // Set this to the largest message size that will be sent including address byte.
\r
101 #define TWI_TWBR 0x4C; // 0x0C // TWI Bit rate Register setting.
\r// Se Application note for detailed
\r// information on setting this value.
\r\r
105 #define ACK (1<<TWI_NACK_BIT )
\r
110 #if defined(__AVR_ATmega328PB__)
\r
112 #define ACK (1<<TWEA)
\r
118 #define TW_STATUS_MASK (_BV(TWS7)|_BV(TWS6)|_BV(TWS5)|_BV(TWS4)|_BV(TWS3))
\r
119 #define TW_STATUS (TWSR_R & TW_STATUS_MASK)
\r
123 #if defined(__AVR_ATmega328P__)
\r
125 #define ACK (1<<TWEA)
\r
127 #define TW_STATUS_MASK (_BV(TWS7)|_BV(TWS6)|_BV(TWS5)|_BV(TWS4)|_BV(TWS3))
\r
128 #define TW_STATUS (TWSR_R & TW_STATUS_MASK)
\r
138 //********** Prototypes **********//
\r
140 void TWI_Master_Initialise( void );
\r
142 unsigned char I2c_WriteByte(unsigned char msg);
\r
143 unsigned char I2c_ReadByte(unsigned char ack_mode);
\r
144 void I2c_StartCondition(void);
\r
145 void I2c_StopCondition(void);
\r