1 // Copyright (c) 2015, Tobias Mueller tm(at)tm3d.de
\r
2 // All rights reserved.
\r
4 // Redistribution and use in source and binary forms, with or without
\r
5 // modification, are permitted provided that the following conditions are
\r
8 // * Redistributions of source code must retain the above copyright
\r
9 // notice, this list of conditions and the following disclaimer.
\r
10 // * Redistributions in binary form must reproduce the above copyright
\r
11 // notice, this list of conditions and the following disclaimer in the
\r
12 // documentation and/or other materials provided with the
\r
14 // * All advertising materials mentioning features or use of this
\r
15 // software must display the following acknowledgement: This product
\r
16 // includes software developed by tm3d.de and its contributors.
\r
17 // * Neither the name of tm3d.de nor the names of its contributors may
\r
18 // be used to endorse or promote products derived from this software
\r
19 // without specific prior written permission.
\r
21 // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
\r
22 // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
\r
23 // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
\r
24 // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
\r
25 // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
\r
26 // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
\r
27 // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
\r
28 // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
\r
29 // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
\r
30 // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
\r
31 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
\r
36 #define OW_PORT _SFR_IO_ADDR(PORTB) //1 Wire Port
\r
37 #define OW_PIN _SFR_IO_ADDR(PINB) //1 Wire Pin as number
\r
38 #define OW_PINN PORTB2
\r
39 #define OW_DDR _SFR_IO_ADDR(DDRB) //pin direction register
\r
40 #define TCNT_REG _SFR_IO_ADDR(TCNT0)
\r
42 #define DB_PORT _SFR_IO_ADDR(PORTB) //1 Wire Port
\r
43 #define DB_PIN _SFR_IO_ADDR(PINB) //1 Wire Pin as number
\r
44 #define DB_PINN PORTB1
\r
46 #define SETZEROMARKER sbi _SFR_IO_ADDR(DDRB),5
\r
47 #define RESETZEROMARKER cbi _SFR_IO_ADDR(DDRB),5
\r
48 #define TESTZEROMARKER sbic _SFR_IO_ADDR(DDRB),5
\r
50 ;#define sdb sbi _SFR_IO_ADDR(PORTB),1
\r
51 ;#define cdb cbi _SFR_IO_ADDR(PORTB),1
\r
53 #define TIMER_INTERRUPT TIM0_OVF_vect
\r
54 #define PIN_INTERRIPT INT0_vect
\r
58 #define OWT_MIN_RESET 70
\r
59 #define OWT_RESET2 40
\r
60 #define OWT_RESET_PRESENT 15
\r
61 #define OWT_PRESENT 50
\r
62 #define OWT_WRITE 18
\r
67 #define OWT_MIN_RESET 140
\r
68 #define OWT_RESET2 80
\r
69 #define OWT_RESET_PRESENT 30
\r
70 #define OWT_PRESENT 130
\r
71 #define OWT_WRITE 35
\r
77 .macro CLEAR_TOV_FLAG
\r
78 ldi r_temp,(1<<TOV0)
\r
79 out _SFR_IO_ADDR(TIFR),r_temp
\r
83 in r_temp, _SFR_IO_ADDR(TIFR)
\r
84 sbrc r_temp,TOV0 ; wenn ueberlauf gleiich weiter
\r
87 .macro CLEAR_INTERRUPT_FLAG
\r
88 ldi r_temp,(1<<INTF0);inerrupt flags durch 1 loeschen..... 0 macht nix
\r
89 out _SFR_IO_ADDR(GIFR),r_temp
\r
93 in r_temp,_SFR_IO_ADDR(TIMSK)
\r
94 sbr r_temp,(1<<TOIE0)
\r
95 out _SFR_IO_ADDR(TIMSK),r_temp
\r
96 ldi r_temp,(1<<TOV0) ;inerrupt flags durch 1 loeschen..... 0 macht nix
\r
97 out _SFR_IO_ADDR(TIFR),r_temp
\r
101 in r_temp,_SFR_IO_ADDR(TIMSK)
\r
102 cbr r_temp,(1<<TOIE0)
\r
103 out _SFR_IO_ADDR(TIMSK),r_temp
\r
108 in r_temp,_SFR_IO_ADDR(MCUCR)
\r
109 ori r_temp,(1<<ISC01)
\r
110 out _SFR_IO_ADDR(MCUCR),r_temp
\r
114 .macro SET_FALLING_RESET_SLEEP
\r
115 in r_temp,_SFR_IO_ADDR(MCUCR)
\r
116 ori r_temp,(1<<ISC01)
\r
117 andi r_temp,~(1<<SM1)
\r
118 out _SFR_IO_ADDR(MCUCR),r_temp
\r
123 ;set clock to 8 MHz
\r
125 out _SFR_IO_ADDR(CLKPR),r_temp
\r
127 ldi r_temp,(1<<CLKPS0)
\r
131 out _SFR_IO_ADDR(CLKPR),r_temp
\r
134 out _SFR_IO_ADDR(TIMSK),r_temp ;; is default
\r
136 ldi r_temp,(1<<INT0)
\r
137 out _SFR_IO_ADDR(GIMSK),r_temp
\r
138 ;Set Timerclock to Clock / 8 (2us)
\r
139 ldi r_temp,(1<<CS01)
\r
140 out _SFR_IO_ADDR(TCCR0B),r_temp
\r
142 cbi OW_DDR,OW_PINN ;; is default....
\r
144 ldi r_temp,(1<<ISC01)
\r
145 out _SFR_IO_ADDR(MCUCR),r_temp
\r