--- /dev/null
+#ifndef TWI_MASTER_H\r
+#define TWI_MASTER_H\r
+#include<avr/io.h> \r
+//********** Defines **********//\r
+\r
+// Defines controlling timing limits\r
+#define TWI_FAST_MODE\r
+#ifdef __4MHZ__\r
+#define SYS_CLK 4000.0 // [kHz]\r
+#else\r
+#define SYS_CLK 8000.0 // [kHz]\r
+#endif\r
+\r
+\r
+\r
+#ifdef TWI_FAST_MODE // TWI FAST mode timing limits. SCL = 100-400kHz\r
+ #define T2_TWI ((SYS_CLK *1300) /1000000) +1 // >1,3us\r
+ #define T4_TWI ((SYS_CLK * 600) /1000000) +1 // >0,6us\r
+ \r
+#else // TWI STANDARD mode timing limits. SCL <= 100kHz\r
+ #define T2_TWI ((SYS_CLK *4700) /1000000) +1 // >4,7us\r
+ #define T4_TWI ((SYS_CLK *4000) /1000000) +1 // >4,0us\r
+#endif\r
+\r
+// Defines controling code generating\r
+//#define PARAM_VERIFICATION\r
+//#define NOISE_TESTING\r
+//#define SIGNAL_VERIFY\r
+\r
+//USI_TWI messages and flags and bit masks\r
+//#define SUCCESS 7\r
+//#define MSG 0\r
+/****************************************************************************\r
+ Bit and byte definitions\r
+****************************************************************************/\r
+#define TWI_READ_BIT 0 // Bit position for R/W bit in "address byte".\r
+#define TWI_ADR_BITS 1 // Bit position for LSB of the slave address bits in the init byte.\r
+#define TWI_NACK_BIT 0 // Bit position for (N)ACK bit.\r
+\r
+#define USI_TWI_NO_DATA 0x00 // Transmission buffer is empty\r
+#define USI_TWI_DATA_OUT_OF_BOUND 0x01 // Transmission buffer is outside SRAM space\r
+#define USI_TWI_UE_START_CON 0x02 // Unexpected Start Condition\r
+#define USI_TWI_UE_STOP_CON 0x03 // Unexpected Stop Condition\r
+#define USI_TWI_UE_DATA_COL 0x04 // Unexpected Data Collision (arbitration)\r
+#define USI_TWI_NO_ACK_ON_DATA 0x05 // The slave did not acknowledge all data\r
+#define USI_TWI_NO_ACK_ON_ADDRESS 0x06 // The slave did not acknowledge the address\r
+#define USI_TWI_MISSING_START_CON 0x07 // Generated Start Condition not detected on bus\r
+#define USI_TWI_MISSING_STOP_CON 0x08 // Generated Stop Condition not detected on bus\r
+\r
+// Device dependant defines\r
+\r
+#if defined(__AVR_AT90Mega169__) | defined(__AVR_ATmega169PA__) | \\r
+ defined(__AVR_AT90Mega165__) | defined(__AVR_ATmega165__) | \\r
+ defined(__AVR_ATmega325__) | defined(__AVR_ATmega3250__) | \\r
+ defined(__AVR_ATmega645__) | defined(__AVR_ATmega6450__) | \\r
+ defined(__AVR_ATmega329__) | defined(__AVR_ATmega3290__) | \\r
+ defined(__AVR_ATmega649__) | defined(__AVR_ATmega6490__)\r
+ #define DDR_USI DDRE\r
+ #define PORT_USI PORTE\r
+ #define PIN_USI PINE\r
+ #define PORT_USI_SDA PORTE5\r
+ #define PORT_USI_SCL PORTE4\r
+ #define PIN_USI_SDA PINE5\r
+ #define PIN_USI_SCL PINE4\r
+#endif\r
+\r
+#if defined(__AVR_ATtiny25__) | defined(__AVR_ATtiny45__) | defined(__AVR_ATtiny85__) | \\r
+ defined(__AVR_AT90Tiny26__) | defined(__AVR_ATtiny26__)\r
+ #define DDR_USI DDRB\r
+ #define PORT_USI PORTB\r
+ #define PIN_USI PINB\r
+ #define PORT_USI_SDA PORTB0\r
+ #define PORT_USI_SCL PORTB2\r
+ #define PIN_USI_SDA PINB0\r
+ #define PIN_USI_SCL PINB2\r
+#endif\r
+\r
+#if defined(__AVR_AT90Tiny2313__) | defined(__AVR_ATtiny2313__)\r
+ #define DDR_USI DDRB\r
+ #define PORT_USI PORTB\r
+ #define PIN_USI PINB\r
+ #define PORT_USI_SDA PORTB5\r
+ #define PORT_USI_SCL PORTB7\r
+ #define PIN_USI_SDA PINB5\r
+ #define PIN_USI_SCL PINB7\r
+#endif\r
+\r
+#if defined(__AVR_ATtiny84__) | defined(__AVR_ATtiny84A__)\r
+#define DDR_USI DDRA\r
+#define PORT_USI PORTA\r
+#define PIN_USI PINA\r
+#define PORT_USI_SDA PORTA6\r
+#define PORT_USI_SCL PORTA4\r
+#define PIN_USI_SDA PINA6\r
+#define PIN_USI_SCL PINA4\r
+#endif\r
+\r
+\r
+//****************** ATMEGA TWI without USI\r
+#define TWI_BUFFER_SIZE 4 // Set this to the largest message size that will be sent including address byte.\r
+#define TWI_TWBR 0x4C; // 0x0C // TWI Bit rate Register setting.\r// Se Application note for detailed\r// information on setting this value.\r\r
+\r
+\r
+\r
+#define ACK (1<<TWI_NACK_BIT )\r
+#define NO_ACK 0\r
+\r
+\r
+\r
+#if defined(__AVR_ATmega328PB__)\r
+#undef ACK\r
+#define ACK (1<<TWEA)\r
+\r
+#define TWBR TWBR0\r
+#define TWSR TWSR0\r
+#define TWCR TWCR0\r
+#define TWDR TWDR0\r
+#define TW_STATUS_MASK (_BV(TWS7)|_BV(TWS6)|_BV(TWS5)|_BV(TWS4)|_BV(TWS3))\r
+#define TW_STATUS (TWSR_R & TW_STATUS_MASK)\r
+\r
+#endif\r
+\r
+#if defined(__AVR_ATmega328P__)\r
+#undef ACK\r
+#define ACK (1<<TWEA)\r
+\r
+#define TW_STATUS_MASK (_BV(TWS7)|_BV(TWS6)|_BV(TWS5)|_BV(TWS4)|_BV(TWS3))\r
+#define TW_STATUS (TWSR_R & TW_STATUS_MASK)\r
+\r
+\r
+#endif\r
+\r
+// General defines\r
+#define TRUE 1\r
+#define FALSE 0\r
+\r
+\r
+//********** Prototypes **********//\r
+\r
+void TWI_Master_Initialise( void );\r
+\r
+unsigned char I2c_WriteByte(unsigned char msg);\r
+unsigned char I2c_ReadByte(unsigned char ack_mode);\r
+void I2c_StartCondition(void);\r
+void I2c_StopCondition(void);\r
+\r
+#endif
\ No newline at end of file
tm3d / owSlave2.git / blobdiff